User's Manual

晶訊科技股份有限公司 8F, No. 150, Jian Yi Road, Zhonghe District,
CC&C Technologies, Inc. New Taipei City, Taiwan 235, R.O.C.
Tel: [phone] Fax: [phone]
Version: 1.6
8
Interface Timing Specification
USB Bus during Power On Sequence
The power on flow description:
After main 3.3V ramp up, the internal power on reset is released by power ready detection circuit and the
power management unit will be enabled. The power management unit enables the internal regulator and
clock circuits.
The power management unit also enables the USB circuits.
USB analog circuits attach resisters to indicate the insertion of the USB device.