TECHNICAL MANUAL LSI53C810A PCI to SCSI I/O Processor Version 2.
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Preface This book is the primary reference and technical manual for the LSI Logic LSI53C810A PCI to SCSI I/O Processor. It contains a complete functional description for the product and includes complete physical and electrical specifications. Audience This manual provides reference information on the LSI53C810A PCI to SCSI I/O processor.
• Chapter 6, Instruction Set of the I/O Processor, defines all of the SCSI SCRIPTS instructions that are supported by the LSI53C810A. • Chapter 7, Electrical Characteristics, contains the electrical characteristics and AC timings for the chip. • Appendix A, Register Summary, is a register summary. Related Publications For background please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.
PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 SCSI SCRIPTS™ Processors Programming Guide, Order Number S14044.A Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF. Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.1100.1111.
vi Preface
Contents Chapter 1 Chapter 2 General Description 1.1 TolerANT® Technology 1.2 LSI53C810A Benefits Summary 1.2.1 SCSI Performance 1.2.2 PCI Performance 1.2.3 Integration 1.2.4 Ease of Use 1.2.5 Flexibility 1.2.6 Reliability 1.2.7 Testability Functional Description 2.1 SCSI Core 2.1.1 DMA Core 2.2 SCRIPTS Processor 2.2.1 SDMS Software: The Total SCSI Solution 2.3 Prefetching SCRIPTS Instructions 2.3.1 Opcode Fetch Burst Capability 2.4 PCI Cache Mode 2.4.1 Load and Store Instructions 2.4.2 3.
2.7 Chapter 3 Chapter 4 Interrupt Handling 2.7.1 Polling and Hardware Interrupts PCI Functional Description 3.1 PCI Addressing 3.1.1 Configuration Space 3.1.2 PCI Bus Commands and Functions Supported 3.2 PCI Cache Mode 3.2.1 Support for PCI Cache Line Size Register 3.2.2 Selection of Cache Line Size 3.2.3 Alignment 3.2.4 Memory Read Multiple Command 3.2.5 Unsupported PCI Commands 3.3 Configuration Registers Signal Descriptions 4.1 PCI Bus Interface Signals 4.1.1 System Signals 4.1.
6.5 6.6 6.7 6.8 Chapter 7 Appendix A 6.4.1 First Dword 6.4.2 Second Dword Read/Write Instructions 6.5.1 First Dword 6.5.2 Second Dword 6.5.3 Read-Modify-Write Cycles 6.5.4 Move To/From SFBR Cycles Transfer Control Instructions 6.6.1 First Dword 6.6.2 Second Dword Memory Move Instructions 6.7.1 First Dword 6.7.2 Second Dword 6.7.3 Third Dword 6.7.4 Read/Write System Memory from a SCRIPTS Instruction Load and Store Instructions 6.8.1 First Dword 6.8.2 Second Dword Electrical Characteristics 7.
Figures 1.1 1.2 2.1 2.2 2.3 2.4 4.1 4.2 5.1 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.
7.21 7.22 7.23 7.24 Target Asynchronous Send Target Asynchronous Receive Initiator and Target Synchronous Transfers 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2) 7-29 7-30 7-30 7-34 2.1 2.2 2.3 3.1 3.2 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 5.1 5.2 5.
7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 A.1 A.
Chapter 1 General Description Chapter 1 is divided into the following sections: • Section 1.1, “TolerANT® Technology” • Section 1.2, “LSI53C810A Benefits Summary” The LSI53C810A PCI to SCSI I/O processor brings high-performance I/O solutions to host adapter, workstation, and general computer designs, making it easy to add SCSI to any PCI system. The LSI53C810A is a pin-for-pin replacement for the LSI53C810 PCI to SCSI I/O processor.
Software development tools are available to developers who use the SCSI SCRIPTS language to create customized SCSI software applications. The LSI53C810A allows easy firmware upgrades and is supported by advanced SCRIPTS commands. 1.1 TolerANT® Technology The LSI53C810A features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers.
1.2 LSI53C810A Benefits Summary This section provides an overview of the LSI53C810A features and benefits. It contains these topics: • SCSI Performance • PCI Performance • Integration • Ease of Use • Flexibility • Reliability • Testability 1.2.1 SCSI Performance To improve SCSI performance, the LSI53C810A: • Complies with PCI 2.
1.2.2 PCI Performance To improve PCI performance, the LSI53C810A: • Bursts 2, 4, 8, or 16 Dwords across PCI bus with 80-byte DMA FIFO • Prefetches up to 8 Dwords of SCRIPTS instructions • Supports 32-bit word data bursts with variable burst lengths. • Bursts SCRIPTS opcode fetches across the PCI bus • Performs zero wait-state bus master data bursts faster than 110 Mbytes/s (@ 33 MHz) • Supports PCI Cache Line Size register 1.2.
• Three programmable SCSI timers: Select/Reselect, Handshake-toHandshake, and General Purpose. The time-out period is programmable from 100 µs to greater than 1.6 seconds • SDMS software for complete PC-based operating system support • Support for relative jump • New SCSI Selected As ID (SSAID) bits for use when responding with multiple IDs 1.2.
• Controlled bus assertion times (reduces RFI, improves reliability, and eases FCC certification) • Latch-up protection greater than 150 mA • Voltage feed-through protection (minimum leakage current through SCSI pads) • High proportion (> 25%) of pins power and ground • Power and ground isolation of I/O pads and internal chip logic • TolerANT technology, which provides: – Active negation of SCSI Data, Parity, Request, and Acknowledge signals for improved fast SCSI transfer rates.
Figure 1.
Figure 1.
Chapter 2 Functional Description Chapter 2 is divided into the following sections: • Section 2.1, “SCSI Core” • Section 2.2, “SCRIPTS Processor” • Section 2.3, “Prefetching SCRIPTS Instructions” • Section 2.4, “PCI Cache Mode” • Section 2.5, “Parity Options” • Section 2.6, “SCSI Bus Interface” • Section 2.7, “Interrupt Handling” The LSI53C810A contains three functional blocks: the SCSI Core, the DMA Core, and the SCRIPTS Processor.
and diagnostic procedures. In support of loopback diagnostics, the SCSI core can perform a self-selection and operate as both an initiator and a target. The SCSI core is controlled by the integrated SCRIPTS processor through a high-level logical interface. Commands controlling the SCSI core are fetched out of the main host memory or local memory.
A complete set of development tools is available for writing custom drivers with SCSI SCRIPTS. For more information on SCSI SCRIPTS instructions supported by the LSI53C810A, see Chapter 6, “Instruction Set of the I/O Processor.” 2.2.1 SDMS Software: The Total SCSI Solution For users who do not need to develop custom drivers, LSI Logic provides a total SCSI solution in PC environments with SDMS software.
the prefetch unit contents, use the No Flush Memory to Memory Move (NFMMOV) instruction for all MMOV operations that do not modify code within the next 4 to 8 Dwords. For more information on this instruction, refer to Chapter 6, “Instruction Set of the I/O Processor.” • On every Store instruction. The Store instruction may also be used to place modified code directly into memory.
Write and Invalidate are each software enabled or disabled to allow the user full flexibility in using these commands. For more information on PCI cache mode operations, refer to Chapter 3, “PCI Functional Description.” 2.4.1 Load and Store Instructions The LSI53C810A supports the Load and Store instruction type, which simplifies the movement of data between memory and the internal chip registers.
Table 2.1 Bits Used for Parity Control and Observation BIt Name Location Description Assert SATN/ on Parity Errors SCSI Control Zero (SCNTL0), Bit 1 Causes the LSI53C810A to automatically assert SATN/ when it detects a parity error while operating as an initiator. Enable Parity Checking SCSI Control Zero (SCNTL0), Bit 3 Enables the LSI53C810A to check for parity errors. The LSI53C810A checks for odd parity.
Table 2.2 SCSI Parity Control EPC AESP Description 0 0 Does not check for parity errors. Parity is generated when sending SCSI data. Asserts odd parity when sending SCSI data. 0 1 Does not check for parity errors. Parity is generated when sending SCSI data. Asserts even parity when sending SCSI data. 1 0 Checks for odd parity on SCSI data received. Parity is generated when sending SCSI data. Asserts odd parity when sending SCSI data. 1 1 Checks for odd parity on SCSI data received.
2.5.1 DMA FIFO The DMA FIFO is divided into four sections, each one byte wide and 20 transfers deep. The DMA FIFO is illustrated in Figure 2.1. Figure 2.1 DMA FIFO Sections 32-bits Wide 20 Bytes Deep 8-bits Byte Lane 3 8-bits Byte Lane 2 8-bits Byte Lane 1 8-bits Byte Lane 0 2.5.1.1 Data Paths The data path through the LSI53C810A is dependent on whether data is being moved into or out of the chip, and whether SCSI data is being transferred asynchronously or synchronously. Figure 2.
Asynchronous SCSI Send – Step 1. Look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC) registers and calculate if there are bytes left in the DMA FIFO. To make this calculation, subtract the seven least significant bits of the DMA Byte Counter (DBC) register from the 7-bit value of the DMA FIFO (DFIFO) register. AND the result with 0x7F for a byte count between zero and 80. Step 2.
Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) register to determine if any bytes are left in the SCSI Input Data Latch (SIDL) register. If bit 7 is set in SSTAT0, then the SCSI Input Data Latch (SIDL) register is full. Synchronous SCSI Receive – Step 1. Subtract the seven least significant bits of the DMA Byte Counter (DBC) register from the 7-bit value of the DMA FIFO (DFIFO) register. AND the result with 0x7F for a byte count between zero and 80. Step 2.
2.6 SCSI Bus Interface The LSI53C810A supports SE operation only. All SCSI signals are active LOW. The LSI53C810A contains the SE output drivers and can be connected directly to the SCSI bus. Each output is isolated from the power supply to ensure that a powered-down LSI53C810A has no effect on an active SCSI bus (CMOS “voltage feed-through” phenomena). TolerANT technology provides signal filtering at the inputs of SREQ/ and SACK/ to increase immunity to signal reflections. 2.6.
Once a change in operating mode occurs, the initiator SCRIPTS should start with a Set Initiator instruction or the target SCRIPTS should start with a Set Target instruction. The Selection and Reselection Enable bits (SCSI Chip ID (SCID) bits 5 and 6, respectively) should both be asserted so that the LSI53C810A may respond as an initiator or as a target. If only selection is enabled, the LSI53C810A cannot be reselected as an initiator.
2.6.3 Synchronous Operation The LSI53C810A can transfer synchronous SCSI data in both the initiator and target modes. The SCSI Transfer (SXFER) register controls both the synchronous offset and the transfer period. It may be loaded by the CPU before SCRIPTS execution begins, from within SCRIPTS using a Table Indirect I/O instruction, or with a Read-Modify-Write instruction.
2.6.3.3 SCNTL3 Register, Bits [2:0] (CCF[2:0]) The CCF[2:0] bits select the frequency of the SCLK for asynchronous SCSI operations. To meet the SCSI timings as defined by the ANSI specification, these bits need to be set properly. 2.6.3.4 SXFER Register, Bits [7:5] (TP[2:0]) The TP[2:0] divider (XFERP) bits determine the SCSI synchronous send rate in either initiator or target mode. This value further divides the output from the SCF divider. 2.6.3.
Figure 2.4 Determining the Synchronous Transfer Rate SCF2 SCF1 SCF0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 SCF Divisor 1 1.5 2 3 3 TP2 0 0 0 0 1 1 1 1 This point must not exceed 50 MHz TP1 TP0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Divide by 4 SCF Divider Synchronous Divider CCF Divider Asynchronous SCSI Logic XFERP Divisor 4 5 6 7 8 9 10 11 Receive Clock Send Clock (to SCSI Bus) SCLK CCF2 0 0 0 0 1 CCF1 0 0 1 1 0 CCF0 0 1 0 1 0 SCSI Clock (MHz) 50.1-66.00 16.67-25.00 25.01-37.50 37.51-50.00 50.
that could be used for other system tasks. The preferred method of detecting interrupts in most systems is hardware interrupts. In this case, the LSI53C810A asserts the Interrupt Request (IRQ/) line that interrupts the microprocessor, causing the microprocessor to execute an interrupt service routine. A hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.7.1.
If the LSI53C810A is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs, data could be left in the DMA FIFO. Because of this the DMA FIFO Empty (DFE) bit in DMA Status (DSTAT) should be checked. If this bit is cleared, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits before continuing. The CLF bit is bit 2 in Chip Test Three (CTEST3). The CSF bit is bit 1 in SCSI Test Three (STEST3). DSTAT – The DMA Status (DSTAT) register contains the DMA-type interrupt bits.
2.7.1.2 Fatal vs. Nonfatal Interrupts A fatal interrupt, as the name implies, always causes SCRIPTS to stop running. All nonfatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit. Interrupt masking is discussed in Section 2.7.1.3, “Masking.” All DMA interrupts (indicated by the DIP bit in ISTAT and one or more bits in DSTAT being set) are fatal.
whether polling or hardware interrupts are being used; whether the interrupt is fatal or nonfatal; and whether the chip is operating in the Initiator or Target mode. If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS do not stop, the appropriate bit in the SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt Status One (SIST1) is still set, the SIP bit in the Interrupt Status (ISTAT) is not set, and the IRQ/ pin is not asserted. See Section 2.7.1.2, “Fatal vs.
interrupts are cleared, all the interrupts that came in afterward move into SIST0, SIST1, and DSTAT. After the first interrupt is cleared by reading the appropriate register, the IRQ/ pin is deasserted for a minimum of three CLKs; the stacked interrupts move into SIST0, SIST1, or DSTAT; and the IRQ/ pin is asserted once again. Since a masked nonfatal interrupt does not set the SIP or DIP bits, interrupt stacking does not occur.
• If the DMA direction is a write to memory and a SCSI interrupt occurs, the LSI53C810A attempts to flush the DMA FIFO to memory before halting. Under any other circumstances only the current cycle is completed before halting, so the DFE bit in DMA Status (DSTAT) should be checked to see if any data remains in the DMA FIFO. • SCSI SREQ/SACK handshakes that have begun are completed before halting. • The LSI53C810A attempts to clean up any outstanding synchronous offset before halting.
consecutive reads to ensure that the interrupts clear properly. Both the SCSI and DMA interrupt conditions should be handled before leaving the ISR. It is recommended that the DMA interrupt is serviced before the SCSI interrupt, because a serious DMA interrupt condition could influence how the SCSI interrupt is acted upon. 6. When using polled interrupts, go back to Step 1 before leaving the ISR, in case any stacked interrupts moved in when the first interrupt was cleared.
Chapter 3 PCI Functional Description Chapter 3 is divided into the following sections: • Section 3.1, “PCI Addressing” • Section 3.2, “PCI Cache Mode” • Section 3.3, “Configuration Registers” 3.1 PCI Addressing There are three types of PCI-defined address space: • Configuration space • Memory space • I/O space 3.1.1 Configuration Space Configuration space is a contiguous 256-byte set of addresses dedicated to each “slot” or “stub” on the bus.
The LSI53C810A operating registers are available in both the upper and lower 128-byte portions of the 256-byte space selected. At initialization time, each PCI device is assigned a base address for memory and I/O accesses. In the case of the LSI53C810A, the upper 24 bits of the address are selected. On every access, the LSI53C810A compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase.
3.1.2.3 Memory Read Command The Memory Read reads data from an agent mapped in memory address space. All 32 address bits are decoded. 3.1.2.4 Memory Read Multiple Command The Memory Read Multiple command reads data from an agent mapped in memory address space. All 32 address bits are decoded. 3.1.2.5 Memory Read Line Command The Memory Read Line command reads data from an agent mapped in memory address space. All 32 address bits are decoded. 3.1.2.
3.2.2 Selection of Cache Line Size The cache logic selects a cache line size based on the values for the burst size in the DMA Mode (DMODE) register and the PCI Cache Line Size register. Note: The LSI53C810A does not automatically use the value in the PCI Cache Line Size register as the cache line size value.
3.2.3.2 Memory Write and Invalidate Command The Memory Write and Invalidate command is identical to the Memory Write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is to say, the master intends to write all bytes within the addressed cache line in a single PCI transaction unless interrupted by the target. This command requires implementation of the PCI Cache Line Size register at address 0x0C in PCI configuration space.
finish the transfer at a later time using another bus ownership. If the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached. PCI Target Retry – During a Write and Invalidate transfer, if the target device issues a retry (STOP with no TRDY, indicating that no data was transferred), the LSI53C810A relinquishes the bus and immediately tries to finish the transfer on another bus ownership.
If cache mode is enabled, a Read Line command is issued on all read cycles, except opcode fetches, when the following conditions are met: • The CLSE (Cache Line Size Enable, bit 7, DMA Control (DCNTL) register) and ERL (Enable Read Line, bit 3, DMA Mode (DMODE) register) bits are set. • The Cache Line Size register must contain a legal burst size value (2, 4, 8 or 16) and that value is less than or equal to the DMA Mode (DMODE) burst size.
When these conditions are met, the chip issues a Read Multiple command instead of a Memory Read during all PCI read cycles. Burst Size Selection – The Read Multiple command reads in multiple cache lines of data in a single bus ownership. The number of cache lines to read is determined by the DMA Mode (DMODE) burst size bits. In other words, the chip switches its normal operating burst size to reflect the DMA Mode (DMODE) burst size settings for the Read Multiple command.
Table 3.
Note: The configuration register descriptions are provided for general information only, to indicate which PCI configuration addresses are supported in the LSI53C810A. For detailed information, refer to the PCI Specification. All PCI-compliant devices, such as the LSI53C810A, must support the Vendor ID, Device ID, Command, and Status registers. Support of other PCI-compliant registers is optional. In the LSI53C810A, registers that are not supported are not writable and return all zeros when read.
Register: 0x00 Vendor ID Read Only 15 0 VID 1 1 1 1 VID 0 0 0 0 0 0 0 0 0 0 0 0 Vendor ID [15:0] This field identifies the manufacturer of the device. The Vendor ID is 0x1000. Register: 0x02 Device ID Read Only 15 0 DID 0 0 0 0 DID 0 0 0 0 0 0 0 0 0 0 0 Device ID This field identifies the particular device. The LSI53C810A device ID is 0x0001.
3-12 R Reserved SE SERR/ Enable 8 This bit enables the SERR/ driver. SERR/ is disabled when this bit is cleared. The default value of this bit is zero. This bit and bit 6 must be set to report address parity errors. R Reserved EPER Enable Parity Error Response 6 This bit allows the LSI53C810A to detect parity errors on the PCI bus and report these errors to the system. Only data parity checking is enabled. The LSI53C810A always generates parity for the PCI bus.
EIS Enable I/O Space 0 This bit controls the LSI53C810A’s response to I/O space accesses. A value of zero disables the response. A value of one allows the LSI53C810A to respond to I/O space accesses at the address specified in Base Address Zero (I/O). Register: 0x06 Status Read/Write 15 14 13 12 DPE SSE RMA RTA 0 0 0 0 11 10 R DT[1:0] 9 0 0 0 8 7 0 DPR 0 R 0 0 0 0 0 0 0 0 The Status register is used to record status information for PCI bus-related events.
RTA Received Target Abort (from Master) 12 A master device should set this bit whenever its transaction is terminated with a target abort. All master devices should implement this bit. R Reserved DT[1:0] DEVSEL/ Timing These bits encode the timing of DEVSEL/. 11 0b00 Fast 0b01 Medium 0b10 Slow 0b11 Reserved [10:9] These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write.
Register: 0x08 Revision ID Read Only 7 0 RID LSI53C810A 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 LSI53C810 0 RID Revision ID [7:0] This register specifies device and revision identifiers. In the LSI53C810A, the upper nibble is 0001b. The lower nibble represents the current revision level of the device. It should have the same value as the Chip Revision Level bits in the Chip Test Three (CTEST3) register.
Register: 0x0C Cache Line Size Read/Write 7 0 CLS 0 0 CLS 0 0 0 0 0 0 Cache Line Size [7:0] This register specifies the system cache line size in units of 32-bit words. Cache mode is enabled and disabled by the Cache Line Size Enable (CLSE) bit, bit 7 in the DMA Control (DCNTL) register. Setting this bit causes the LSI53C810A to align to cache line boundaries before allowing any bursting, except during MMOVs in which the read and write addresses are Burst Size boundary misaligned.
Register: 0x0E Header Type Read Only 7 0 HT 0 0 HT 0 0 0 0 0 0 Header Type [7:0] This register identifies the layout of bytes 0x10 through 0x3F in configuration space and also whether or not the device contains multiple functions. The value of this register is 0x00.
Register: 0x3C Interrupt Line Read/Write 7 0 IL 0 0 IL 0 0 0 0 0 0 Interrupt Line [7:0] This register is used to communicate interrupt line routing information. POST software writes the routing information into this register as it initiates and configures the system. The value in this register tells which input of the system interrupt controller(s) the device’s interrupt pin is connected to. Values in this register are specified by system architecture.
Register: 0x3E Min_Gnt Read Only 7 0 MG 0 0 MG 0 1 0 0 0 1 Min_Gnt [7:0] This register is used to specify the desired settings for Latency Timer values. Min_Gnt is used to specify how long a burst period the device needs. The value specified in this register is in units of 0.25 microseconds. Values of zero indicate that the device has no major requirements for the settings of Latency Timers. The LSI53C810A sets the Min_Gnt register to 0x11.
3-20 PCI Functional Description
Chapter 4 Signal Descriptions This chapter presents the LSI53C810A pin configuration and signal definitions using tables and illustrations. Figure 4.1 is the pin diagram and Figure 4.2 is a functional signal grouping. The pin definitions are presented in Table 4.1 through Table 4.8. The LSI53C810A is pin-for-pin compatible with the LSI53C810. This chapter is divided into the following sections: • Section 4.1, “PCI Bus Interface Signals” • Section 4.
LSI53C810A Pin Diagram 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 AD22 VSS-I AD23 IDSEL C_BE3/ AD24 AD25 VSS-I AD26 AD27 VDD-I AD28 AD29 VSS-I AD30 AD31 VDD-C REQ/ GNT VSS-C Figure 4.
Signals are assigned a type. There are four signal types: I Input, a standard input only signal. O Output, a standard output driver (typically a Totem Pole Output). T/S 3-state, a bidirectional, 3-state input/output signal. S/T/S Sustained 3-state, an active LOW 3-state signal owned and driven by one and only one agent at a time. Table 4.1 describes the Power and Ground Signals group. Table 4.1 Power and Ground Signals Name Pin No.
Figure 4.
4.1 PCI Bus Interface Signals The PCI signal definitions are organized into the following functional groups: Power and Ground Signals, System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, and Error Reporting Signals. 4.1.1 System Signals Table 4.2 describes the System Signals group. Table 4.2 System Signals Name Pin No. Type Description CLK 80 I Clock provides timing for all transactions on the PCI bus and is an input to every PCI device.
4.1.2 Address and Data Signals Table 4.3 describes the Address and Data Signals group. Table 4.3 Address and Data Signals Name Pin No. Type Description AD[31:0] 85, 86, 88, 89, 91, 92, 94, 95, 98, 100, 1, 2, 4, 6, 7, 8, 23, 24, 25, 27, 29, 30, 31, 33, 35, 36, 38, 39, 41, 42, 44, 45 T/S Physical Dword Address and Data are multiplexed on the same PCI pins. During the first clock of a transaction, AD[31:0] contain a physical byte address. During subsequent clocks, AD[31:0] contain data.
4.1.3 Interface Control Signals Table 4.4 describes the Interface Control Signals group. Table 4.4 Name Interface Control Signals Pin No. Type Description FRAME/ 11 S/T/S Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME/ is asserted to indicate that a bus transaction is beginning. While FRAME/ is asserted, data transfers continue. While FRAME/ is deasserted, either the transaction is in the final data phase or the bus is idle.
4.1.4 Arbitration Signals Table 4.5 describes the Arbitration Signals group. Table 4.5 Arbitration Signals Name Pin No. Type Strength Description REQ/ 200, A4 O 16 mA PCI Request indicates to the system arbiter that this agent desires use of the PCI bus. This is a point-to-point signal. Every master has its own REQ/ signal. GNT/ 199, B5 I N/A Grant indicates to the agent that access to the PCI bus has been granted. This is a point-to-point signal. Every master has its own GNT/ signal. 4.1.
4.2 SCSI Bus Interface Signals The SCSI signal definitions are organized into the following functional groups: SCSI Bus Interface Signals and Additional Interface Signals. 4.2.1 SCSI Bus Interface Signals Table 4.7 describes the SCSI Bus Interface Signals group. Table 4.7 SCSI Bus Interface Signals Name Pin No. SCLK 51 SD[7:0], SDP SCTRL/ Type Description I SCSI Clock is used to derive all SCSI-related timings. The speed of this clock is determined by the application requirements.
4.2.2 Additional Interface Signals Table 4.8 describes the Additional Interface Signals group. Table 4.8 Additional Interface Signals Name Pin No. Type Description TESTIN/ 52 I Test In. When this pin is driven LOW, the LSI53C810A connects all inputs and outputs to an “AND tree.” The SCSI control signals and data lines are not connected to the “AND tree.” The output of the “AND tree” is connected to the Test Out pin.
Table 4.8 Additional Interface Signals (Cont.) Name Pin No. Type Description MAC/_ TESTOUT 53 T/S Memory Access Control. This pin can be programmed to indicate local or system memory accesses (non-PCI applications). It is also used to test the connectivity of the LSI53C810A signals using an “AND tree” scheme. The MAC/_TESTOUT pin is only driven as the Test Out function when the TESTIN/ pin is driven LOW. IRQ/ 47 O Interrupt.
4-12 Signal Descriptions
Chapter 5 Operating Registers This chapter describes all LSI53C810A operating registers. Table 5.1, the register map, lists registers by operating and configuration addresses. The terms “set” and “assert” are used to refer to bits that are programmed to a binary one. Similarly, the terms “deassert,” “clear,” and “reset” are used to refer to bits that are programmed to a binary zero. Any bits marked as reserved should always be written to zero; mask all information read from them.
Figure 5.
ARB[1:0] Arbitration Mode Bits 1 and 0 ARB1 ARB0 Arbitration Mode 0 0 Simple arbitration 0 1 Reserved 1 0 Reserved 1 1 Full arbitration, selection/reselection [7:6] Simple Arbitration 1. The LSI53C810A waits for a bus free condition to occur. 2. It asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) register) onto the SCSI bus.
5-4 4. The LSI53C810A repeats arbitration until it wins control of the SCSI bus. When it wins, the Won Arbitration bit is set in the SCSI Status Zero (SSTAT0) register, bit 2. 5. The LSI53C810A performs selection by asserting the following onto the SCSI bus: SSEL/, the target’s ID (stored in the SCSI Destination ID (SDID) register), and the LSI53C810A’s ID (stored in the SCSI Chip ID (SCID) register). 6.
EPC Enable Parity Checking 3 When this bit is set, the SCSI data bus is checked for odd parity when data is received from the SCSI bus in either the initiator or target mode. If a parity error is detected, bit 0 of the SCSI Interrupt Status Zero (SIST0) register is set and an interrupt may be generated. If the LSI53C810A is operating in the initiator mode and a parity error is detected, assertion of SATN/ is optional, but the transfer continues until the target changes phase.
Register: 0x01 (0x81) SCSI Control One (SCNTL1) Read/Write 5-6 7 6 5 4 3 2 1 0 EXC ADB DHP CON RST AESP IARB SST 0 0 0 0 0 0 0 0 EXC Extra Clock Cycle of Data Setup 7 When this bit is set, an extra clock period of data setup is added to each SCSI data transfer. The extra data setup time can provide additional system design margin, though it affects the SCSI transfer rates. Clearing this bit disables the extra clock cycle of data setup time.
When this bit is set, the LSI53C810A does not halt the SCSI transfer when SATN/ or a parity error is received. CON Connected 4 This bit is automatically set any time the LSI53C810A is connected to the SCSI bus as an initiator or as a target. It is set after the LSI53C810A successfully completes arbitration or when it has responded to a bus-initiated selection or reselection. This bit is also set after the chip wins simple arbitration when operating in low level mode.
bit is cleared automatically when the selection or reselection sequence is completed, or times out. Interrupts do not occur until after this bit is reset. An unexpected disconnect condition clears IARB without it attempting arbitration. See the SCSI Disconnect Unexpected bit (SCSI Control Two (SCNTL2), bit 7) for more information on expected versus unexpected disconnects. It is possible to abort an immediate arbitration sequence. First, set the Abort bit in the Interrupt Status (ISTAT) register.
Register: 0x02 (0x82) SCSI Control Two (SCNTL2) Read/Write 7 6 0 R SDU 0 x x x x x x x SDU SCSI Disconnect Unexpected 7 This bit is valid in the initiator mode only. When this bit is set, the SCSI core is not expecting the SCSI bus to enter the Bus Free phase. If it does, an unexpected disconnect error is generated (see the Unexpected Disconnect bit in the SCSI Interrupt Status Zero (SIST0) register, bit 2).
determines the transfer rate. For example, if SCLK is 40 MHz and the SCF value is set to divide by one, then the maximum synchronous receive rate is 10 Mbytes/s ((40/1) /4 = 10). For synchronous send, the output of this divider gets divided by the transfer period (XFERP) bits in the SCSI Transfer (SXFER) register, and that value determines the transfer rate. For valid combinations of the SCF and XFERP, see Table 5.2. Table 5.
Table 5.2 Asynchronous Clock Conversion Factor CCF2 CCF1 CCF0 SCSI Clock (MHz) 0 0 0 50.01–66.00 0 0 1 16.67–25.00 0 1 0 25.01–37.50 0 1 1 37.51–50.00 1 0 0 50.01–66.
R Reserved [4:3] ENC[2:0] Encoded LSI53C810A Chip SCSI ID [2:0] These bits are used to store the LSI53C810A encoded SCSI ID. This is the ID which the chip asserts when arbitrating for the SCSI bus. The IDs that the LSI53C810A responds to when being selected or reselected are configured in the Response ID (RESPID) register.
TP2 TP1 TP0 XFERP 0 0 0 4 0 0 1 5 0 1 0 6 0 1 1 7 1 0 0 8 1 0 1 9 1 1 0 10 1 1 1 11 Use the following formula to calculate the synchronous send and receive rates. Table 5.3 and Table 5.4 show examples of possible bit combinations. Synchronous Send Rate = (SCLK/SCF)/XFERP Synchronous Receive Rate = (SCLK/SCF) /4 Where: Table 5.
Table 5.3 Examples of Synchronous Transfer Periods and Rates for SCSI-1 (Cont.) Synch. SCF ÷ XFERP Synch. Synch. Receive Synch. SCLK SCNTL3 SXFER Send Rate Send Rate Receive (MHz) Bits [6:4] Bits [7:5] (Mbytes/s) Period (ns) (Mbytes/s) Period (ns) 40 2 4 5 200 5 200 37.50 1.5 4 6.25 160 6.25 160 33.33 1.5 4 5.55 180 5.55 180 25 1 4 6.25 160 6.25 160 20 1 4 5 200 5 200 16.67 1 4 4.17 240 4.17 240 Table 5.
the LSI53C810A. These bits determine the LSI53C810A’s method of transfer for Data-In and Data-Out phases only; all other information transfers occur asynchronously. Table 5.
Register: 0x07 (0x87) General Purpose (GPREG) Read/Write 7 2 1 R x x x 0 GPIO[1:0] x x x 0 0 R Reserved [7:2] GPIO[1:0] General Purpose [1:0] These bits are programmed through the General Purpose Pin Control (GPCNTL) register as inputs, outputs, or to perform special functions. These signals can also be programmed as live inputs and sensed through a SCRIPTS register to register Move Instruction. GPIO[1:0] default as inputs. When configured as inputs, an internal pull-up is enabled.
Register: 0x08 (0x88) SCSI First Byte Received (SFBR) Read/Write 7 0 IB 0 0 0 0 0 0 0 0 This register contains the first byte received in any asynchronous information transfer phase. For example, when the a LSI53C810A is operating in initiator mode, this register contains the first byte received in Message-In, Status phase, Reserved-In and Data-In.
Register: 0x09 (0x89) SCSI Output Control Latch (SOCL) Read/Write 7 6 5 4 3 2 1 0 REQ ACK BSY SEL ATN MSG C/D I/O 0 0 0 0 0 0 0 0 REQ Assert SCSI REQ/ Signal 7 ACK Assert SCSI ACK/ Signal 6 BSY Assert SCSI BSY/ Signal 5 SEL Assert SCSI SEL/ Signal 4 ATN Assert SCSI ATN/ Signal 3 MSG Assert SCSI MSG/ Signal 2 C/D Assert SCSI C_D/ Signal 1 I/O Assert SCSI I_O/ Signal 0 This register is used primarily for diagnostic testing or programmed I/O operation.
Register: 0x0A (0x8A) SCSI Selector ID (SSID) Read Only 7 6 3 VAL 0 2 R x x 0 ENID[2:0] x x 0 0 0 VAL SCSI Valid Bit 7 If VAL is asserted, then the two SCSI IDs are detected on the bus during a bus-initiated selection or reselection, and the encoded destination SCSI ID bits below are valid. If VAL is deasserted, only one ID is present and the contents of the encoded destination ID are meaningless.
Register: 0x0B (0x8B) SCSI Bus Control Lines (SBCL) Read Only 7 6 5 4 3 2 1 0 REQ ACK BSY SEL ATN MSG C/D I/O x x x x x x x x REQ SREQ/ Status 7 ACK SACK/ Status 6 BSY SBSY/ Status 5 SEL SSEL/ Status 4 ATN SATN/ Status 3 MSG SMSG/ Status 2 C/D SC_D/ Status 1 I/O SI_O/ Status 0 This register returns the SCSI control line status. A bit is set when the corresponding SCSI control line is asserted.
in the Interrupt Status (ISTAT) register is also cleared. It is possible to mask DMA interrupt conditions individually through the DMA Interrupt Enable (DIEN) register. When performing consecutive 8-bit reads of the DMA Status (DSTAT), SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers (in any order), insert a delay equivalent to 12 CLK periods between the reads to ensure that the interrupts clear properly.
R Reserved 1 IID Illegal Instruction Detected This status bit is set any time an illegal instruction is detected, whether the LSI53C810A is operating in single step mode or automatically executing SCSI SCRIPTS. 0 Any of the following conditions during instruction execution also set this bit: • The LSI53C810A is executing a Wait Disconnect instruction and the SCSI REQ line is asserted without a disconnect occurring. • A Move, Chained Move, or Memory Move command with a byte count of zero is fetched.
OLF SODL Full 5 This bit is set when SCSI Output Data Latch (SODL) contains data. The SCSI Output Data Latch (SODL) register is the interface between the DMA logic and the SCSI bus. In synchronous mode, data is transferred from the host bus to the SCSI Output Data Latch (SODL) register, and then to the SCSI Output Data Register (SODR, a hidden buffer register which is not accessible) before being sent to the SCSI bus.
Register: 0x0E (0x8E) SCSI Status One (SSTAT1) Read Only 7 4 FF[3:0] 0 FF[3:0] 0 0 3 2 1 0 SDPL MSG C/D I/O x x x x 0 FIFO Flags [7:4] These four bits define the number of bytes that currently reside in the LSI53C810A’s SCSI synchronous data FIFO. These bits are not latched and they will change as data moves through the FIFO. The FIFO can hold up to 9 bytes. Values over nine will not occur.
MSG SCSI MSG/ Signal 2 C/D SCSI C_D/ Signal 1 I/O SCSI I_O/ Signal 0 These three SCSI phase status bits (MSG, C/D, and I/O) are latched on the asserting edge of SREQ/ when operating in either initiator or target mode. These bits are set when the corresponding signal is active. They are useful when operating in the low level mode.
Registers: 0x10–0x13 (0x90–0x93) Data Structure Address (DSA) Read/Write 31 0 DSA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 DSA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data Structure Address [31:0] This 32-bit register contains the base address used for all table indirect calculations. The DSA register is usually loaded prior to starting an I/O, but it is possible for a SCRIPTS Memory Move to load the DSA during the I/O.
3. Read the Interrupt Status (ISTAT) register. 4. If the SCSI Interrupt Pending bit is set, then read the SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt Status One (SIST1) register to determine the cause of the SCSI Interrupt and go back to Step 2. 5. If the SCSI Interrupt Pending bit is clear, and the DMA Interrupt Pending bit is set, then write 0x00 value to this register. 6.
also notify the LSI53C810A of a predefined condition and the SCRIPTS processor may take action while SCRIPTS are executing. CON Connected 3 This bit is automatically set any time the LSI53C810A is connected to the SCSI bus as an initiator or as a target. It is set after successfully completing selection or when the LSI53C810A responds to a bus-initiated selection or reselection. It is also set after the LSI53C810A wins arbitration when operating in low level mode.
• A SCSI gross error occurs • An unexpected disconnect occurs • A SCSI reset occurs • A parity error is detected • The handshake-to-handshake timer is expired • The general purpose timer is expired To determine exactly which condition(s) caused the interrupt, read the SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers. DIP DMA Interrupt Pending 0 This status bit is set when an interrupt condition is detected in the DMA portion of the LSI53C810A.
Register: 0x19 (0x99) Chip Test One (CTEST1) Read Only 7 4 3 0 FMT[3:0] 1 1 FFL[3:0] 1 1 0 0 0 0 FMT[3:0] Byte Empty in DMA FIFO [7:4] These bits identify the bottom bytes in the DMA FIFO that are empty. Each bit corresponds to a byte lane in the DMA FIFO. For example, if byte lane three is empty, then FMT3 will be set. Since the FMT flags indicate the status of bytes at the bottom of the FIFO, if all FMT bits are set, the DMA FIFO is empty.
SIGP Signal Process 6 This bit is a copy of the SIGP bit in the Interrupt Status (ISTAT) register (bit 5). The SIGP bit is used to signal a running SCRIPTS instruction. When this register is read, the SIGP bit in the Interrupt Status (ISTAT) register is cleared. CIO Configured as I/O 5 This bit is defined as the Configuration I/O Enable Status bit. This read only bit indicates if the chip is currently enabled as I/O space. Note: CM Both bits 4 and 5 may be set if the chip is dual-mapped.
Register: 0x1B (0x9B) Chip Test Three (CTEST3) Read/Write 7 4 V[3:0] x x x x 3 2 1 0 FLF CLF FM WRIE 0 0 0 0 V[3:0] Chip Revision Level [7:4] These bits identify the chip revision level for software purposes. FLF Flush DMA FIFO 3 When this bit is set, data residing in the DMA FIFO is transferred to memory, starting at the address in the DMA Next Address (DNAD) register.
WRIE Write and Invalidate Enable 0 This bit, when set, causes issuing of Memory Write and Invalidate commands on the PCI bus whenever legal. These conditions are described in more detail in Chapter 3, “PCI Functional Description.
when an interrupt occurs. These bits are unstable while data is being transferred between the two cores; once the chip has stopped transferring data, these bits are stable. The DMA FIFO (DFIFO) register counts the number of bytes transferred between the DMA core and the SCSI core. The DMA Byte Counter (DBC) register counts the number of bytes transferred across the host bus. The difference between these two counters represents the number of bytes remaining in the DMA FIFO.
ZMOD High Impedance Mode 6 Setting this bit causes the LSI53C810A to place all output and bidirectional pins into a high impedance state. In order to read data out of the LSI53C810A, clear this bit. This bit is intended for board-level testing only. Do not set this bit during normal system operation. ZSD SCSI Data High Impedance 5 Setting this bit causes the LSI53C810A to place the SCSI data bus SD[7:0] and the parity line (SDP) in a high impedance state.
FBL[2:0] FIFO Byte Control FBL2 FBL1 [2:0] FBL0 DMA FIFO Byte Lane Pins x x x Disabled N/A 0 0 0 0 D[7:0] 0 0 1 1 D[15:8] 0 1 0 2 D[23:16] 0 1 1 3 D[31:24] These bits steer the contents of the Chip Test Six (CTEST6) register to the appropriate byte lane of the 32-bit DMA FIFO. If the FBL2 bit is set, then FBL1 and FBL0 determine which of four byte lanes can be read or written.
contents and the current DNAD value. This bit automatically clears itself after decrementing the DMA Byte Counter (DBC) register. R Reserved 5 MASR Master Control for Set or Reset Pulses 4 This bit controls the operation of bit 3. When this bit is set, bit 3 asserts the corresponding signals. When this bit is cleared, bit 3 deasserts the corresponding signals. Do not change this bit and bit 3 in the same write cycle.
Chip Test Four (CTEST4) register. Writes to this register while the test mode is not enabled produces unexpected results. Registers: 0x24–0x26 (0xA4–0xA6) DMA Byte Counter (DBC) Read/Write 23 0 DBC x x x x x x x DBC x x x x x x x x x x x x x x x x x DMA Byte Counter [23:0] This 24-bit register determines the number of bytes transferred in a Block Move instruction. While sending data to the SCSI bus, the counter is decremented as data is moved into the DMA FIFO from memory.
Register: 0x27 (0xA7) DMA Command (DCMD) Read/Write 7 0 DCMD x x DCMD x x x x x x DMA Command [7:0] This 8-bit register determines the instruction for the LSI53C810A to execute. This register has a different format for each instruction. For a complete description, see Chapter 6, “Instruction Set of the I/O Processor.
the first SCRIPTS instruction is written to this register, SCRIPTS instructions are automatically fetched and executed until an interrupt condition occurs. In single step mode, there is a single step interrupt after each instruction is executed. The DMA SCRIPTS Pointer (DSP) register does not need to be written with the next address, but the Start DMA bit (bit 2, DMA Control (DCNTL) register) must be set each time the step interrupt occurs to fetch and execute the next SCRIPTS command.
Registers: 0x34–0x37 (0xB4–0xB7) Scratch Register A (SCRATCHA) Read/Write 31 0 SCRATCHA x x x x x x x x x x x x SCRATCHA x x x x x x x x x x x x x x x x x x x x Scratch Register A [31:0] This is a general purpose, user-definable scratch pad register. Apart from CPU access, only Register Read/Write and Memory Moves into the SCRATCH register alter its contents. The power-up value of this register is indeterminate.
SIOM BL1 BL0 Burst Length 0 0 2-transfer burst 0 1 4-transfer burst 1 0 8-transfer burst 1 1 16-transfer burst Source I/O Memory Enable 5 This bit is defined as an I/O Memory Enable bit for the source address of a Memory Move or Block Move Command. If this bit is set, then the source address is in I/O space; and if cleared, then the source address is in memory space. This function is useful for register-to-memory operations using the Memory Move instruction when the LSI53C810A is I/O mapped.
ERMP Enable Read Multiple 2 Setting this bit causes Read Multiple commands to be issued on the PCI bus after certain conditions have been met. These conditions are described in Chapter 3, “PCI Functional Description.” BOF Burst Opcode Fetch Enable 1 Setting this bit causes the LSI53C810A to fetch instructions in burst mode, if the Burst Disable bit (Chip Test Four (CTEST4), bit7) is cleared. Specifically, the chip bursts in the first two Dwords of all instructions using a single bus ownership.
Register: 0x39 (0xB9) DMA Interrupt Enable (DIEN) Read/Write 7 6 5 4 3 2 1 0 R MDPE BF ABRT SSI SIR R IID x 0 0 0 0 0 x 0 This register contains the interrupt mask bits corresponding to the interrupting conditions described in the DMA Status (DSTAT) register. An interrupt is masked by clearing the appropriate mask bit. Masking an interrupt prevents IRQ/ from being asserted for the corresponding interrupt, but the status bit is still set in the DMA Status (DSTAT) register.
Register: 0x3A (0xBA) Scratch Byte Register (SBR) Read/Write 7 0 SBR 0 0 SBR 0 0 0 0 0 0 Scratch Byte Register [7:0] This is a general purpose register. Apart from CPU access, only register Read/Write and Memory Moves into this register alters its contents. The default value of this register is zero. This register is called the DMA Watchdog Timer on previous LSI53C8XX family products.
SSM Single Step Mode 4 Setting this bit causes the LSI53C810A to stop after executing each SCRIPTS instruction, and generate a single step interrupt. When this bit is cleared the LSI53C810A does not stop after each instruction. It continues fetching and executing instructions until an interrupt condition occurs. For normal SCSI SCRIPTS operation, keep this bit clear.
assert. As with any register other than Interrupt Status (ISTAT), this register cannot be accessed except by a SCRIPTS instruction during SCRIPTS execution. COM LSI53C700 Family Compatibility 0 When this bit is cleared, the LSI53C810A behaves in a manner compatible with the LSI53C700 family; selection/reselection IDs are stored in both the SCSI Selector ID (SSID) and SCSI First Byte Received (SFBR) registers.
Register: 0x40 (0xC0) SCSI Interrupt Enable Zero (SIEN0) Read/Write 7 6 5 4 3 2 1 0 M/A CMP SEL RSL SGE UDC RST PAR 0 0 0 0 0 0 0 0 This register contains the interrupt mask bits that correspond to the interrupting conditions described in the SCSI Interrupt Status Zero (SIST0) register. An interrupt is masked by clearing the appropriate mask bit. For more information on interrupts, see Chapter 2, “Functional Description.
• Data underflow – reading the SCSI FIFO when no data was present. • Data overflow – writing to the SCSI FIFO while it is full. • Offset underflow – receiving a SACK/ pulse in target mode before the corresponding SREQ/ is sent. • Offset overflow – receiving an SREQ/ pulse in the initiator mode, and exceeding the maximum offset (defined by the MO[3:0] bits in the SCSI Transfer (SXFER) register). • A phase change in the initiator mode, with an outstanding SREQ/SACK offset.
Register: 0x41 (0xC1) SCSI Interrupt Enable One (SIEN1) Read/Write 7 3 R x x x x x 2 1 0 STO GEN HTH 0 0 0 This register contains the interrupt mask bits corresponding to the interrupting conditions described in the SCSI Interrupt Status One (SIST1) register. An interrupt is masked by clearing the appropriate mask bit. For more information on interrupts, refer to Chapter 2, “Functional Description.
Register: 0x42 (0xC2) SCSI Interrupt Status Zero (SIST0) Read Only 7 6 5 4 3 2 1 0 M/A CMP SEL RSL SGE UDC RST PAR 0 0 0 0 0 0 0 0 Reading the SCSI Interrupt Status Zero (SIST0) register returns the status of the various interrupt conditions, whether they are enabled in the SCSI Interrupt Enable Zero (SIEN0) register or not. Each bit set indicates an occurrence of the corresponding condition. Reading the SCSI Interrupt Status Zero (SIST0) clears the interrupt status.
SEL Selected 5 This bit is set when the LSI53C810A is selected by another SCSI device. The Enable Response to Selection bit must be set in the SCSI Chip ID (SCID) register (and the Response ID (RESPID) register must hold the chip’s ID) for the LSI53C810A to respond to selection attempts. RSL Reselected 4 This bit is set when the LSI53C810A is reselected by another SCSI device.
when the LSI53C810A operates in the initiator mode. When the LSI53C810A operates in low level mode, any disconnect causes an interrupt, even a valid SCSI disconnect. This bit is also set if a selection time-out occurs (it may occur before, at the same time, or stacked after the STO interrupt, since this is not considered an expected disconnect).
R Reserved [7:3] STO Selection or Reselection Time-out 2 When the SCSI device which the LSI53C810A is attempting to select or reselect does not respond within the programmed time-out period. See the description of the SCSI Timer Zero (STIME0) register, bits [3:0], for more information on the time-out timer. GEN General Purpose Timer Expired 1 This bit is set when the general purpose timer expires. The time measured is the time between enabling and disabling of the timer.
Data Bytes Running SLPAR – 00000000 1. 11001100 11001100 (XOR of word 1) 2. 01010101 10011001 (XOR of word 1 and 2) 3. 00001111 10010110 (XOR of word 1, 2 and 3) Even parity >>> 10010110 4. 10010110 00000000 A one in any bit position of the final SCSI Longitudinal Parity (SLPAR) value would indicate a transmission error. The SCSI Longitudinal Parity (SLPAR) register is also used to generate the check bytes for SCSI send operations.
When bits 3 through 0 are set, the corresponding access is considered local and the MAC/_TESTOUT pin is driven high. When these bits are cleared, the corresponding access is to far memory and the MAC/_TESTOUT pin is driven low. This function is enabled after a Transfer Control SCRIPTS instruction is executed. DWR DataWR 3 This bit is used to define if a data write is considered to be a local memory access. DRD DataRD 2 This bit is used to define if a data read is considered to be a local memory access.
FE Fetch Enable 6 The internal opcode fetch signal is presented on GPIO0 if this bit is set, regardless of the state of bit 0 (GPIO0_EN). R Reserved 5 GPIO_EN[1:0] GPIO Enable [1:0] These bits power up set, causing the GPIO1 and GPIO0 pins to become inputs. Resetting these bits causes GPIO[1:0] to become outputs.
HTH[7:4], SEL[3:0], GEN[3:0]1 Minimum Timeout (40 MHz) Minimum Timeout (50 MHz) 0110 4 ms 3.2 ms 0111 8 ms 6.4 ms 1000 16 ms 12.8 ms 1001 32 ms 25.6 ms 1010 64 ms 51.2 ms 1011 128 ms 102.4 ms 1100 256 ms 204.8 ms 1101 512 ms 409.6 ms 1110 1.024 s 819.2 ms 1111 2.048 s 1.6384 s 1. These values are correct if the CCF bits in the SCSI Control Three (SCNTL3) register are set according to the valid combinations in the bit description.
GEN bit in the SCSI Interrupt Status One (SIST1) register is set. Refer to the table under SCSI Timer Zero (STIME0), bits [3:0], for the available time-out periods. Note: To reset a timer before it expires and obtain repeatable delays, the time value must be written to zero first, and then written back to the desired value. This is also required when changing from one time value to another. See Chapter 2, “Functional Description,” for an explanation of how interrupts are generated when the timers expire.
Register: 0x4C (0xCC) SCSI Test Zero (STEST0) Read Only 7 6 4 R x 5-60 SSAID x x x 3 2 1 0 SLT ART SOZ SOM 0 x 1 1 R Reserved SSAID SCSI Selected As ID [6:4] These bits contain the encoded value of the SCSI ID that the LSI53C810A is selected or reselected as during a SCSI selection or reselection phase. These bits are read only and contain the encoded value of 0–7 possible IDs that could be used to select the LSI53C810A.
SOM SCSI Synchronous Offset Maximum 0 This bit indicates that the current synchronous SREQ/SACK offset is the maximum specified by bits [3:0] in the SCSI Transfer (SXFER) register. This bit is not latched and may change at any time. It is used in low level synchronous SCSI operations. When this bit is set, the LSI53C810A, as a target, is waiting for the initiator to acknowledge the data transfers. If the LSI53C810A is an initiator, then the target has sent the offset number of requests.
Register: 0x4E (0xCE) SCSI Test Two (STEST2) Read/Write 7 6 5 4 3 2 1 0 SCE ROF R SLB SZM R EXT LOW 0 0 x 0 0 x 0 0 SCE SCSI Control Enable 7 Setting this bit allows assertion of all SCSI control and data lines through the SCSI Output Control Latch (SOCL) and SCSI Output Data Latch (SODL) registers regardless of whether the LSI53C810A is configured as a target or initiator. Note: 5-62 Do not set this bit during normal operation, since it could cause contention on the SCSI bus.
R Reserved EXT Extend SREQ/SACK Filtering 1 LSI Logic TolerANT SCSI receiver technology includes a special digital filter on the SREQ/ and SACK/ pins which causes the disregarding of glitches on deasserting edges. Setting this bit increases the filtering period from 30 ns to 60 ns on the deasserting edge of the SREQ/ and SACK/ signals. Note: Never set this bit during fast SCSI (greater than 5 megatransfers per second) operations, because a valid assertion could be treated as a glitch.
LSI53C810A is in an information transfer phase. TolerANT active negation should be enabled to improve setup and deassertion times at fast SCSI timings. Active negation is disabled after reset or when this bit is cleared. For more information on TolerANT technology, refer to Chapter 1, “General Description.” 5-64 STR SCSI FIFO Test Read 6 Setting this bit places the SCSI core into a test mode in which the SCSI FIFO is easily read.
SCSI Input Data Latch (SIDL), SCSI Output Data Latch (SODL), and SODR full bits in the SCSI Status Zero (SSTAT0) register are cleared. STW SCSI FIFO Test Write 0 Setting this bit places the SCSI core into a test mode in which the FIFO is easily written. While this bit is set, writes to the SCSI Output Data Latch (SODL) register cause the entire word contained in this register to be loaded into the FIFO.
Registers: 0x54 (0xD4) SCSI Output Data Latch (SODL) Read/Write 15 0 SODL x x x x SODL x x x x x x x x x x x x SCSI Output Data Latch [15:0] This register is used primarily for diagnostic testing or programmed I/O operation. Data written to this register is asserted onto the SCSI data bus by setting the Assert Data Bus bit in the SCSI Control One (SCNTL1) register. This register is used to send data using programmed I/O. Data flows through this register when sending data in any mode.
Chapter 6 Instruction Set of the I/O Processor This chapter is divided into the following sections: • Section 6.1, “Low Level Register Interface Mode” • Section 6.2, “SCSI SCRIPTS” • Section 6.3, “Block Move Instructions” • Section 6.4, “I/O Instruction” • Section 6.5, “Read/Write Instructions” • Section 6.6, “Transfer Control Instructions” • Section 6.7, “Memory Move Instructions” • Section 6.
6.2 SCSI SCRIPTS To operate in the SCSI SCRIPTS mode, the LSI53C810A requires only a SCRIPTS start address. The start address must be at a Dword (four byte) boundary. This aligns subsequent SCRIPTS at a Dword boundary since all SCRIPTS are 8 or 12 bytes long. All instructions are fetched from external memory. The LSI53C810A fetches and executes its own instructions by becoming a bus master on the host bus and fetching two or three 32-bit words into its registers.
Table 6.1 SCRIPTS Instructions Instruction Description Block Move Block Move instruction moves data between the SCSI bus and memory. I/O or Read/Write I/O or Read/Write instructions cause the LSI53C810A to trigger common SCSI hardware sequences, or to move registers. Transfer Control Transfer Control instruction allows SCRIPTS instructions to make decisions based on real time SCSI bus conditions.
• The LSI53C810A typically fetches two Dwords (64 bits) and decodes the high order byte of the first Dword as a SCRIPTS instruction. If the instruction is a Block Move, the lower three bytes of the first Dword are stored and interpreted as the number of bytes to be moved. The second Dword is stored and interpreted as the 32-bit beginning address in main memory to which the move is directed.
Figure 6.
6.3.1 First Dword IT[1:0] Instruction Type - Block Move [31:30] IA Indirect Addressing 29 When this bit is cleared, user data is moved to or from the 32-bit data start address for the Block Move instruction. The value is loaded into the chip’s address register and incremented as data is transferred. The address of data to be moved is in the second Dword of this instruction. When set, the 32-bit user data start address for the Block Move is the address of a pointer to the actual data buffer address.
Note: TIA Do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. Table Indirect Addressing 28 When this bit is set, the 24-bit signed value in the start address of the move is treated as a relative displacement from the value in the Data Structure Address (DSA) register. Both the transfer count and the source/ destination address are fetched from this location.
Figure 6.
SCRIPTS can directly execute operating system I/O data structures, saving time at the beginning of an I/O operation. The I/O data structure can begin on any Dword boundary and may cross system segment boundaries. There are two restrictions on the placement of pointer data in system memory: • the eight bytes of data in the MOVE instruction must be contiguous, as shown below, and • indirect data fetches are not available during execution of a Memory-to-Memory DMA operation.
– If any other Group Code is received, the DMA Byte Counter (DBC) register is not modified and the LSI53C810A will request the number of bytes specified in the DMA Byte Counter (DBC) register. If the DMA Byte Counter (DBC) register contains 0x000000, an illegal instruction interrupt is generated. 4. The LSI53C810A transfers the number of bytes specified in the DMA Byte Counter (DBC) register starting at the address specified in the DMA Next Address (DNAD) register. 5.
3. The LSI53C810A compares the SCSI phase bits in the DMA Command (DCMD) register with the latched SCSI phase lines stored in the SCSI Status One (SSTAT1) register. These phase lines are latched when SREQ/ is asserted. 4. If the SCSI phase bits match the value stored in the SCSI SCSI Status One (SSTAT1) register, the LSI53C810A transfers the number of bytes specified in the DMA Byte Counter (DBC) register starting at the address pointed to by the DMA Next Address (DNAD) register. 5.
MSG C_D TC[23:0] I_O SCSI Phase 0 0 0 Data-Out 0 0 1 Data-In 0 1 0 Command 0 1 1 Status 1 0 0 Reserved-Out 1 0 1 Reserved-In 1 1 0 Message-Out 1 1 1 Message-In Transfer Counter [23:0] This 24-bit field specifies the number of data bytes to be moved between the LSI53C810A and system memory. The field is stored in the DMA Byte Counter (DBC) register.
indirect addressing, the value in this field is an offset into a table pointed to by the Data Structure Address (DSA). The table entry contains byte count and address information. 6.4 I/O Instruction The I/O SCRIPTS instruction causes the LSI53C810A to trigger common SCSI hardware sequences such as Set/Clear ACK, Set/Clear ATN, Set/Clear Target Mode, Select With ATN, or Wait for Reselect. 6.4.
Reselect Instruction 1. The LSI53C810A arbitrates for the SCSI bus by asserting the SCSI ID stored in the SCSI Chip ID (SCID) register. If it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. 2. If the LSI53C810A wins arbitration, it attempts to reselect the SCSI device whose ID is defined in the destination ID field of the instruction.
Wait Select Instruction 1. If the LSI53C810A is selected, it fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register. 2. If reselected, the LSI53C810A fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the DMA Next Address (DNAD) register. Manually set the LSI53C810A to Initiator mode when it is reselected. 3.
Figure 6.3 illustrates the register bit values that represent an I/O instruction. Figure 6.
Clear Instruction When the SACK/ or SATN/ bits are cleared, the corresponding bits are cleared in the SCSI Output Control Latch (SOCL) register. Do not set SACK/ or SATN/ except for testing purposes. When the target bit is cleared, the corresponding bit in the SCSI Control Zero (SCNTL0) register is cleared. When the carry bit is cleared, the corresponding bit in the ALU is cleared. Note: None of the signals are cleared on the SCSI bus in Target mode.
field stored in the DMA Next Address (DNAD) register. Manually set the LSI53C810A to Initiator mode if it is reselected, or to Target mode if it is selected. 4. If the Select with SATN/ field is set, the SATN/ signal is asserted during the selection phase. Wait Disconnect Instruction 1. The LSI53C810A waits for the Target to perform a “legal” disconnect from the SCSI bus.
Clear Instruction When the SACK/or SATN/ bits are cleared, the corresponding bits are cleared in the SCSI Output Control Latch (SOCL) register. When the target bit is cleared, the corresponding bit in the SCSI Control Zero (SCNTL0) register is cleared. When the Carry bit is cleared, the corresponding bit in the ALU is cleared.
• An I/O command structure must have all four bytes contiguous in system memory, as shown below. The offset/period bits are ordered as in the SCSI Transfer (SXFER) register. The configuration bits are ordered as in the SCSI Control Three (SCNTL3) register. Config ID Offset/period 00 Use this bit only in conjunction with the Select, Reselect, Wait Select, and Wait Reselect instructions.
Table Relative Treats the alternate jump address as a relative jump and fetches the device ID, synchronous offset, and synchronous period indirectly. The value in bits [23:0] of the first four bytes of the SCRIPTS instruction is added to the data structure base address to form the fetch address. Command Table Offset Absolute Jump Offset Sel Select with ATN/ 24 This bit specifies whether SATN/ is asserted during the selection phase when the LSI53C810A is executing a Select instruction.
ACK Set/Clear SACK/ 6 ATN Set/Clear SATN/ 3 These two bits are used in conjunction with a Set or Clear instruction to assert or deassert the corresponding SCSI control signal. Bit 6 controls the SCSI SACK/ signal. Bit 3 controls the SCSI SATN/ signal. Setting either of these bits sets or resets the corresponding bit in the SCSI Output Control Latch (SOCL) register, depending on the instruction used. The Set instruction is used to assert SACK/ and/or SATN/ on the SCSI bus.
6.5 Read/Write Instructions The Read/Write instruction type moves the contents of one register to another, or performs arithmetic operations such as AND, OR, XOR, Addition, and Shift. 6.5.1 First Dword IT[1:0] Instruction Type - Read/Write Instruction [31:30] The Read/Write instruction uses operator bits 26 through 24 in conjunction with the opcode bits to determine which instruction is currently selected.
The Add operation is used to increment or decrement register values (or memory values if used in conjunction with a Memory-to-Register Move operation) for use as loop counters. 6.5.4 Move To/From SFBR Cycles All operations are read-modify-writes. However, two registers are involved, one of which is always the SFBR. The possible functions of this instruction are: 6-24 • Write one byte (value contained within the SCRIPTS instruction) into any chip register.
Figure 6.4 illustrates the register bit values that represent a Read/Write instruction. Figure 6.
Table 6.2 Read/Write Instructions Opcode 111 Read-Modify-Write Opcode 110 Move to SFBR Opcode 101 Move from SFBR 000 Move data into register. Syntax: “Move data8 to RegA” Move data into SCSI First Byte Received (SFBR) register. Syntax: “Move data8 to SFBR” Move data into register. Syntax: “Move data8 to RegA” 0011 Shift register one bit to the left and place the result in the same register.
Table 6.2 Read/Write Instructions Opcode 111 Read-Modify-Write Opcode 110 Move to SFBR Opcode 101 Move from SFBR 110 Add data to register without carry and place the result in the same register. Syntax: “Move RegA + data8 to RegA” Add data to register without carry and place the result in the SCSI First Byte Received (SFBR) register. Syntax: “Move RegA + data8 to SFBR” Add data to SFBR without carry and place the result in the register.
OPC2 OPC1 OPC0 Instruction Defined 0 0 0 Jump 0 0 1 Call 0 1 0 Return 0 1 1 Interrupt 1 x x Reserved Jump Instruction The LSI53C810A can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare and True/False bit fields. If the comparisons are true, then it loads the DMA SCRIPTS Pointer (DSP) register with the contents of the DMA SCRIPTS Pointer Save (DSPS) register.
If the comparisons are false, the LSI53C810A fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register and the instruction pointer is not modified. Return Instruction The LSI53C810A can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare, and True/False bit fields.
Figure 6.5 illustrates the register bit values that represent a Transfer Control instruction. Figure 6.
If the comparisons are false, the LSI53C810A fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register and the instruction pointer is not modified. Interrupt Instruction The LSI53C810A can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare, and True/False bit fields. If the comparisons are true, then the LSI53C810A generates an interrupt by asserting the IRQ/ signal.
RA MSG C/D I/O SCSI Phase 0 0 0 Data-Out 0 0 1 Data-In 0 1 0 Command 0 1 1 Status 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Message-Out 1 1 1 Message-In Relative Addressing Mode 23 When this bit is set, the 24-bit signed value in the DMA SCRIPTS Pointer Save (DSPS) register is used as a relative offset from the current DMA SCRIPTS Pointer (DSP) address (which is pointing to the next instruction, not the one currently executing).
A relative transfer can be to any address within a 16 Mbyte segment. The program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new execution address. SCRIPTS programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing SCRIPTS. For example, major sections of code can be accessed with far calls using the 32-bit physical address, then local labels can be called using relative transfers.
CD Compare Data 18 When this bit is set, the first byte received from the SCSI data bus (contained in SCSI First Byte Received (SFBR) register) is compared with the Data to be Compared Field in the Transfer Control instruction. The Wait for Valid Phase bit controls when this compare occurs. The Jump if True/False bit determines the condition (true or false) to branch on. CP Compare Phase 17 When the LSI53C810A is in Initiator mode, this bit controls phase compare operations.
6.6.2 Second Dword Jump Address [31:0] This 32-bit field contains the address of the next instruction to fetch when a jump is taken. Once the LSI53C810A has fetched the instruction from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the DMA SCRIPTS Pointer (DSP) register and becomes the current instruction pointer.
6.7 Memory Move Instructions This SCRIPTS instruction allows the LSI53C810A to execute high-performance block moves of 32-bit data from one part of main memory to another. In this mode, the LSI53C810A is an independent, high-performance DMA controller irrespective of SCSI operations. Since the registers of the LSI53C810A can be mapped into system memory, this SCRIPTS instruction also moves an LSI53C810A register to or from memory or another LSI53C810A register.
Figure 6.6 illustrates the register bit values that represent a Memory Move instruction. Figure 6.
The DMA SCRIPTS Pointer Save (DSPS) and Data Structure Address (DSA) registers are additional holding registers used during the Memory Move. However, the contents of the Data Structure Address (DSA) register are preserved. 6.7.1 First Dword IT[1:0] Instruction Type - Memory Move Instruction R Reserved [29:25] These bits are reserved and must be zero. If any of these bits is set, an illegal instruction interrupt occurs.
6.7.4 Read/Write System Memory from a SCRIPTS Instruction By using the Memory Move instruction, single or multiple register values may be transferred to or from system memory. Because the LSI53C810A responds to addresses as defined in the Base Address Zero (I/O) or Base Address One (Memory) registers, it can be accessed during a Memory Move operation if the source or destination address decodes to within the chip’s register space.
operating register set of the chip. If it does, a PCI illegal read/write cycle occur, the chip issues an interrupt (Illegal Instruction Detected) immediately following. Bits A1, A0 Number of Bytes Allowed to Load/Store 00 One, two, three or four 01 One, two, or three 10 One or two 11 One The SIOM and DIOM bits in the DMA Mode (DMODE) register determine whether the destination or source address of the instruction is in Memory space or I/O space.
Note: This bit has no effect unless the Prefetch Enable bit in the DMA Control (DCNTL) register is set. For information on SCRIPTS instruction prefetching, see Chapter 2, “Functional Description.” LS Load and Store 24 When this bit is set, the instruction is a Load. When cleared, it is a Store. R Reserved RA[6:0] Register Address [22:16] A[6:0] select the register to Load and Store to/from within the LSI53C810A.
Figure 6.7 illustrates the register bit values that represent a Load and Store instruction. Figure 6.
Chapter 7 Electrical Characteristics This chapter specifies the LSI53C810A electrical and mechanical characteristics. It is divided into the following sections: • Section 7.1, “DC Characteristics” • Section 7.2, “TolerANT Technology” • Section 7.3, “AC Characteristics” • Section 7.4, “PCI Interface Timing Diagrams” • Section 7.5, “PCI Interface Timing” • Section 7.6, “SCSI Timings” • Section 7.7, “Package Drawings” 7.
Table 7.1 Symbol Absolute Maximum Stress Ratings Parameter Min Max Unit Test Conditions TSTG Storage temperature −55 150 °C – VDD Supply voltage −0.5 7.0 V – VIN Input voltage VSS −0.5 VDD +0.5 V – ±150 – mA – – 2K V MIL-STD 883C, Method 3015.7 ILP1 2 ESD Latch-up current Electrostatic discharge 1. − 2 V < VPIN < 8 V. 2. SCSI pins only. Note: Stresses beyond those listed above may cause permanent damage to the device.
Table 7.3 Symbol SCSI Signals—SD[7:0]/, SDP/, SREQ/, SACK/ Parameter Min Max Unit Test Conditions VIH Input high voltage 2.0 VDD +0.5 V – VIL Input low voltage VSS −0.5 0.8 V – VOH1 Output high voltage 2.5 3.5 V 2.5 mA VOL Output low voltage VSS 0.5 V 48 mA IIN Input leakage −10 10 µA – IOZ 3-state leakage −10 10 µA – 1. TolerANT active negation enabled. Table 7.
Table 7.6 Symbol CI CIO Table 7.7 Symbol Capacitance Parameter Min Max Unit Test Conditions Input capacitance of input pads – 7 pF – Input capacitance of I/O pads – 10 pF – Output Signals—MAC/_TESTOUT, REQ/ Parameter Min Max Unit Test Conditions VOH Output high voltage 2.4 VDD V −16 mA VOL Output low voltage VSS 0.4 V 16 mA IOH Output high current −8 – mA VDD −0.5 V IOL Output low current 16 – mA 0.
Table 7.9 Output Signal—SERR/ Symbol Parameter Min Max Unit Test Conditions VOL Output low voltage VSS 0.4 V 16 mA IOL Output low current 16 – mA 0.4 V IOZ 3-state leakage −10 10 µA – Table 7.10 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR/ Symbol Parameter Min Max Unit Test Conditions VIH Input high voltage 2.0 VDD +0.5 V – VIL Input low voltage VSS −0.5 0.8 V – VOH Output high voltage 2.
Table 7.11 Symbol Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/ Parameter Min Max Unit Test Conditions VIH Input high voltage 2.0 VDD +0.5 V – VIL Input low voltage VSS −0.5 0.8 V – VOH Output high voltage 2.4 VDD V −16 mA VOL Output low voltage VSS 0.4 V 16 mA IOH Output high current −8 – mA 2.4 V IOL Output low current 16 – mA 0.
Table 7.12 Symbol TolerANT Technology Electrical Characteristics Parameter Min Max Unit Test Conditions VOH Output high voltage 2.5 3.5 V IOH = 2.5 mA VOL Output low voltage 0.1 0.5 V IOL = 48 mA VIH Input high voltage 2.0 7.0 V – VIL Input low voltage −0.5 0.8 V Referenced to VSS VIK Input clamp voltage −0.66 −0.77 V VDD = 4.75; II = −20 mA VTH Threshold, HIGH to LOW 1.1 1.3 V – VTL Threshold, LOW to HIGH 1.5 1.7 V – 200 400 mV – VOH = 2.
Figure 7.1 Rise and Fall Time Test Conditions 47 Ω + 20 pF 2.5 V − Figure 7.2 SCSI Input Filtering t1 VTH REQ/ or ACK/ Input Note: t1 is the input filtering period. Figure 7.3 Hysteresis of SCSI Receiver 1.1 1.3 Receiving Logic Level 1 0 1.5 1.
Figure 7.4 Input Current as a Function of Input Voltage Input Current (milliAmperes) +40 +20 14.4 V 8.2 V 0 − 0.7 V HIGH-Z OUTPUT −20 ACTIVE −40 −4 0 4 8 12 16 Input Voltage (Volts) Output Current as a Function of Output Voltage 0 −200 −400 −600 −800 0 1 2 3 4 5 Output Voltage (Volts) TolerANT Technology Output Source Current (milliamperes) Output Sink Current (milliamperes) Figure 7.
7.3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to Section 7.1, “DC Characteristics”). Chip timings are based on simulation at worst case voltage, temperature, and processing. Timings were developed with a load capacitance of 50 pF. Table 7.13 and Figure 7.6 provide clock timing data. Table 7.
Table 7.14 and Figure 7.7 provide reset input timing data. Table 7.14 Symbol Reset Input Timing Parameter Min Max Unit t1 Reset pulse width 10 – tCLK t2 Reset deasserted setup to CLK HIGH 0 – ns Figure 7.7 Reset Input CLK t1 t2 RST/ t3 MAD1 t4 Valid Data 1. When enabled. Table 7.15 and Figure 7.8 provide interrupt output timing data. Table 7.
7.4 PCI Interface Timing Diagrams Figure 7.9 through Figure 7.18 represent signal activity when the LSI53C810A accesses the PCI bus. The timings for the PCI bus interface are listed on page 7-26.
7.4.1 Target Timing Figure 7.9 through Figure 7.12 describe target timing. Figure 7.
Figure 7.
Figure 7.
Figure 7.
7.4.2 Initiator Timing Figure 7.13 through Figure 7.18 describe initiator timing. Figure 7.
Figure 7.
Figure 7.
Figure 7.
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Figure 7.
Figure 7.17 Burst Read (Cont.
Figure 7.
Figure 7.18 Burst Write (Cont.
7.5 PCI Interface Timing Table 7.16 describes the PCI timing data for the LSI53C810A. Table 7.
7.6 SCSI Timings Tables 7.17 through 7.23 and Figures 7.19 through 7.23 describe the LSI53C810A SCSI timing data. Table 7.17 Symbol Initiator Asynchronous Send (5 Mbytes/s) Parameter Min Max Unit t1 SACK/ asserted from SREQ/ asserted 10 – ns t2 SACK/ deasserted from SREQ/ deasserted 10 – ns t3 Data setup to SACK/ asserted 55 – ns t4 Data hold from SREQ/ deasserted 20 – ns Figure 7.
Table 7.18 Symbol Initiator Asynchronous Receive (5 Mbytes/s) Parameter Min Max Unit t1 SACK/ asserted from SREQ/ asserted 10 – ns t2 SACK/ deasserted from SREQ/ deasserted 10 – ns t3 Data setup to SREQ/ asserted 0 – ns t4 Data hold from SACK/ asserted 0 – ns Figure 7.
Table 7.19 Symbol Target Asynchronous Send (5 Mbytes/s) Parameter Min Max Unit t1 SACK/ asserted from SREQ/ asserted 10 – ns t2 SACK/ deasserted from SREQ/ deasserted 10 – ns t3 Data setup to SREQ/ asserted 55 – ns t4 Data hold from SACK/ asserted 20 – ns Figure 7.
Table 7.20 Symbol Target Asynchronous Receive (5 Mbytes/s) Parameter Min Max Unit t1 SREQ/ deasserted from SACK/ asserted 10 – ns t2 SREQ/ asserted from SACK/ deasserted 10 – ns t3 Data setup to SREQ/ asserted 0 – ns t4 Data hold from SACK/ asserted 0 – ns Figure 7.22 Target Asynchronous Receive SREQ/ n n+1 t1 SACK/ t2 n+1 n t3 t4 SD[7:0], SDP/ Valid n Valid n + 1 Figure 7.
Table 7.21 Symbol SCSI-1 Transfers (SE, 5.
Table 7.23 Symbol 7-32 SCSI-2 Fast Transfers (10.
7.7 Package Drawings Figure 7.24 illustrates the mechanical drawing for the LSI53C810A.
Figure 7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2) Important: 7-34 This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UD.
Figure 7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 2 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UD.
7-36 Electrical Characteristics
Appendix A Register Summary Table A.1 lists the LSI53C810A configuration registers by register name. Table A.
Table A.2 lists the LSI53C810A SCSI registers by register name. Table A.
Table A.
Table A.
Index Symbols assert SCSI RST/ signal bit 5-7 assert SCSI SEL/ bit 5-18 ATN bit 5-18, 5-20 (AD[31:0]) 4-6 (BARO[31:0]) 3-17 (BARZ[31:0]) 3-17 (CLS[7:0]) 3-16 (FMT) 5-29 (HT[7:0]) 3-17 (IL[7:0]) 3-18 (IP[7:0]) 3-18 (LT[7:0]) 3-16 (MG[7:0]) 3-19 (ML[7:0]) 3-19 B Numerics encoded chip SCSI ID, bits 5-12 3.
clock address incrementor bit 5-36 clock byte counter bit 5-36 clock conversion factor bits 5-10 CLSE bit 5-45 CM bit 5-31 CMP bit 5-48, 5-51 COM bit 5-47 CON bit 5-7, 5-28 configured as I/O bit 5-31 configured as memory bit 5-31 connected bit 5-7, 5-28 CSF bit 5-64 CTEST0 register 5-29 CTEST1 register 5-30 CTEST2 register 5-30 CTEST4 register 5-34 CTEST5 register 5-36 CTEST6 register 5-37 cycle frame 4-7 D DACK bit 5-31 data acknowledge status bit 5-31 data path 2-8 data request status bit 5-31 data struc
I M I/O bit 5-25 I/O instructions 6-13 I_O bit 5-18 IARB bit 5-7 IDSEL 4-7 IID bit 5-22, 5-44 illegal instruction detected bit 5-22, 5-44 immediate arbitration bit 5-7 initialization device select 4-7 initiator mode phase mismatch 5-51 initiator ready 4-7 input 4-3 instructions block move 6-5 I/O 6-13 load and store 6-39 memory move 6-36 read/write 6-23 transfer control 6-27 interrupt line 3-18 pin (IP[7:0]) 3-18 interrupt status register 5-26 interrupt-on-the-fly bit 5-28 interrupts fatal vs.
SCSI bus data lines 5-66 SCSI chip ID 5-11 SCSI control one register 5-6 SCSI control register two 5-9 SCSI control three 5-9 SCSI control zero 5-2 SCSI destination ID 5-15 SCSI first byte received 5-17 SCSI input data latch 5-65 SCSI interrupt enable one 5-50 SCSI interrupt enable zero 5-48 SCSI interrupt status one 5-53 SCSI interrupt status zero 5-51 SCSI longitudinal parity 5-54 SCSI output control latch 5-18 SCSI output data latch 5-66 SCSI selector ID 5-19 SCSI status one 5-24 SCSI status two 5-25 SCS
0x41 5-50 0x42 5-51 0x43 5-53 0x44 5-54 0x46 5-55 0x47 5-56 0x48 5-57 0x49 5-58 0x4A 5-59 0x4C 5-60 0x4D 5-61 0x4E 5-62 0x4F 5-63 0x50 5-65 0x54 5-66 0x58 5-66 PCI configuration registers 0x00 3-11 0x02 3-11 0x04 3-11 0x06 3-13 0x08 3-15 0x09 3-15 0x0C 3-16 0x0D 3-16 0x0E 3-17 0x10 3-17 0x14 3-17 0x3C 3-18 0x3D 3-18 0x3E 3-19 0x3F 3-19 encoded chip SCSI ID, bits 5-12 register bits abort operation 5-26 aborted 5-21, 5-44 arbitration in progress 5-23 arbitration mode 5-3 arbitration priority encoder test 5-60
SCRIPTS interrupt instruction received 5-21, 5-44 SCSI C_D/ signal 5-25 SCSI control enable 5-62 SCSI data high impedance 5-35 SCSI disconnect unexpected 5-9 SCSI FIFO test read 5-64 SCSI FIFO test write 5-65 SCSI gross error 5-48, 5-52 SCSI high impedance mode 5-62 SCSI I_O/ signal 5-25 SCSI interrupt pending 5-28 SCSI isolation 5-61 SCSI loopback mode 5-62 SCSI low level mode 5-63 SCSI MSG/ signal 5-25 SCSI parity error 5-49 SCSI phase mismatch or SCSI ATN condition 5-48 SCSI reset condition 5-49 SCSI RST
SCSI I_O/ bit 5-25 SCSI input data latch register 5-65 SCSI instructions block move 6-5 I/O 6-13 load/store 6-39 memory move 6-36 read/write 6-23 SCSI interrupt enable one register 5-50 SCSI interrupt enable zero register 5-48 SCSI interrupt pending bit 5-28 SCSI interrupt status one register 5-53 SCSI interrupt status zero register 5-51 SCSI isolation bit 5-61 SCSI longitudinal parity register 5-54 SCSI loopback mode bit 5-62 SCSI low level mode 5-63 SCSI MSG/ bit 5-25 SCSI output control latch register 5-
Storage Device Management System (SDMS) 2-3 STR bit 5-64 STW bit 5-65 SXFER register 5-12 synchronous clock conversion factor bits 5-9 synchronous data transfer rate 2-13 synchronous operation 2-13 SZM bit 5-62 T target mode SATN/ active 5-51 target mode bit 5-5 target ready 4-7 TE bit 5-63 TEMP register 5-33 temporary register 5-33 TEOP bit 5-31 termination 2-11 testability 1-6 timer test mode bit 5-64 timing diagrams 7-12 PCI interface 7-26 SCSI timings 7-27 timings PCI 7-26 SCSI 7-27 TolerANT 1-2 enable
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