TECHNICAL MANUAL LSI53C875A PCI to Ultra SCSI Controller Version 2.
This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited. Document DB14-000143-01, Second Edition (December 2000).
Preface This book is the primary reference and technical manual for the LSI53C875A PCI to Ultra SCSI Controller. It contains a complete functional description for the product and also includes complete physical and electrical specifications. Audience This manual provides reference information on the LSI53C875A PCI to Ultra SCSI Controller.
• Chapter 6, Electrical Specifications contains the electrical characteristics and AC timing diagrams. • Appendix A, Register Summary is a register summary. • Appendix B, External Memory Interface Diagram Examples contains several example interface drawings for connecting the LSI53C875A to external ROMs. Related Publications For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.
PCI Special Interest Group 2575 N.E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF. Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.1100.1111.
vi Preface
Contents Chapter 1 Chapter 2 General Description 1.1 New Features in the LSI53C875A 1.2 Benefits of Ultra SCSI 1.3 TolerANT® Technology 1.4 LSI53C875A Benefits Summary 1.4.1 SCSI Performance 1.4.2 PCI Performance 1.4.3 Integration 1.4.4 Ease of Use 1.4.5 Flexibility 1.4.6 Reliability 1.4.7 Testability Functional Description 2.1 PCI Functional Description 2.1.1 PCI Addressing 2.1.2 PCI Bus Commands and Functions Supported 2.1.3 PCI Cache Mode 2.2 SCSI Functional Description 2.2.1 SCRIPTS Processor 2.2.
2.3 2.4 2.5 Chapter 3 viii 2.2.11 Parity Options 2.2.12 DMA FIFO 2.2.13 SCSI Bus Interface 2.2.14 Select/Reselect During Selection/Reselection 2.2.15 Synchronous Operation 2.2.16 Interrupt Handling 2.2.17 Chained Block Moves Parallel ROM Interface Serial EEPROM Interface 2.4.1 Default Download Mode 2.4.2 No Download Mode Power Management 2.5.1 Power State D0 2.5.2 Power State D1 2.5.3 Power State D2 2.5.4 Power State D3 Signal Descriptions 3.1 LSI53C875A Functional Signal Grouping 3.
Chapter 4 Chapter 5 Chapter 6 Registers 4.1 PCI Configuration Registers 4.2 SCSI Registers 4.3 64-Bit SCRIPTS Selectors 4.4 Phase Mismatch Jump Registers SCSI SCRIPTS Instruction Set 5.1 Low Level Register Interface Mode 5.2 High Level SCSI SCRIPTS Mode 5.2.1 Sample Operation 5.3 Block Move Instruction 5.3.1 First Dword 5.3.2 Second Dword 5.4 I/O Instruction 5.4.1 First Dword 5.4.2 Second Dword 5.5 Read/Write Instructions 5.5.1 First Dword 5.5.2 Second Dword 5.5.3 Read-Modify-Write Cycles 5.5.
6.3 6.4 6.5 6.6 AC Characteristics PCI and External Memory Interface Timing Diagrams 6.4.1 Target Timing 6.4.2 Initiator Timing 6.4.3 External Memory Timing SCSI Timing Diagrams Package Diagrams Appendix A Register Summary Appendix B External Memory Interface Diagram Examples 6-9 6-11 6-13 6-19 6-35 6-52 6-58 Index Customer Feedback Figures 1.1 1.2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.1 5.1 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.
6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.29 6.30 6.31 6.32 6.33 6.34 6.35 6.36 6.37 6.38 6.39 B.1 B.
B.3 B.4 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 ns Memory 512 Kbyte Interface with 150 ns Memory B-3 B-4 Tables 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 4.1 4.2 4.3 4.4 4.5 4.6 5.
5.2 5.3 5.4 5.5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.
6.30 6.31 6.32 6.33 6.34 6.35 6.36 6.37 6.38 6.39 6.40 6.41 6.42 6.43 6.44 6.45 A.1 A.2 xiv External Memory Write Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle Slow Memory (≤ 128 Kbytes) Read Cycle Slow Memory (≤ 128 Kbytes) Write Cycle ≤= 64 Kbytes ROM Read Cycle ≤ 64 Kbyte ROM Write Cycle Initiator Asynchronous Send Initiator Asynchronous Receive Target Asynchronous Send Target Asynchronous Receive SCSI-1 Transfers (5.
Chapter 1 General Description Chapter 1 is divided into the following sections: • Section 1.1, “New Features in the LSI53C875A” • Section 1.2, “Benefits of Ultra SCSI” • Section 1.3, “TolerANT® Technology” • Section 1.4, “LSI53C875A Benefits Summary” The LSI53C875A PCI to Ultra SCSI Controller brings Ultra SCSI performance to host adapter, workstation, and general computer designs, making it easy to add a high-performance SCSI bus to any PCI system.
Figure 1.1 Typical LSI53C875A System Application PCI Bus Interface Controller PCI Bus SCSI Bus LSI53C875A PCI to Wide Ultra SCSI Controller Fixed Disk, Optical Disk Printer, Tape, and Other Peripherals Processor Bus PCI Graphic Accelerator PCI Fast Ethernet Memory Controller Central Processing Unit (CPU) Figure 1.
1.1 New Features in the LSI53C875A The LSI53C875A is a drop-in replacement for the LSI53C875 PCI to Ultra SCSI Controller, with these additional benefits: • Supports 32-bit PCI Interface with 64-bit addressing. • Handles SCSI phase mismatches in SCRIPTS without interrupting the CPU. • Supports JTAG boundary scanning. • Supports PC99 Power Management. – Automatically downloads Subsystem Vendor ID, Subsystem ID, and PCI power management levels D0, D1, D2, and D3.
synchronous negotiations for Ultra SCSI rates and to enable the clock quadrupler. Chapter 2, “Functional Description,” contains more information on Ultra SCSI design. 1.3 TolerANT® Technology The LSI53C875A features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators.
• Ease of Use • Flexibility • Reliability • Testability 1.4.1 SCSI Performance To improve SCSI performance, the LSI53C875A: • Has integrated SE transceivers. • Bursts up to 512 bytes across the PCI bus through its 944 byte FIFO. • Performs wide, Ultra SCSI synchronous transfers as fast as 40 Mbytes/s. • Can handle phase mismatches in SCRIPTS without interrupting the system processor, eliminating the need for CPU intervention during an I/O disconnect/reselect sequence.
• Supports additional arithmetic capability with the Expanded Register Move instruction. 1.4.2 PCI Performance To improve PCI performance, the LSI53C875A: • Complies with PCI 2.2 specification. • Supports 32-bit 33 MHz PCI interface with 64-bit addressing. • Supports dual address cycles which can be generated for all SCRIPTS for > 4 Gbyte addressability. • Bursts 2, 4, 8, 16, 32, 64, or 128 Dword transfers across the PCI bus. • Supports 32-bit word data bursts with variable burst lengths.
• Up to one megabyte of add-in memory support for BIOS and SCRIPTS storage. • Reduced SCSI development effort. • Compiler-compatible with existing LSI53C7XX and LSI53C8XX family SCRIPTS. • Direct connection to PCI and SCSI SE. • Development tools and sample SCSI SCRIPTS available. • Five GPIO pins. • Maskable and pollable interrupts. • Wide SCSI, A or P cable, and up to 15 devices supported. • Three programmable SCSI timers: Select/Reselect, Handshake-to-Handshake, and General Purpose.
• SCSI clock quadrupler bits enable Ultra SCSI transfer rates with a 20 or 40 MHz SCSI clock input. • Selectable IRQ pin disable bit. • Ability to route system clock to SCSI clock. • Compatible with 3.3 V and 5 V PCI. 1.4.6 Reliability Enhanced reliability features of the LSI53C875A include: • 2 kV ESD protection on SCSI signals. • Protection against bus reflections due to impedance mismatches. • Controlled bus assertion times (reduces RFI, improves reliability, and eases FCC certification).
Chapter 2 Functional Description Chapter 2 is divided into the following sections: • Section 2.1, “PCI Functional Description” • Section 2.2, “SCSI Functional Description” • Section 2.3, “Parallel ROM Interface” • Section 2.4, “Serial EEPROM Interface” • Section 2.
Figure 2.1 LSI53C875A Block Diagram PCI Bus 32 Bit PCI Interface, PCI Configuration Register Wide Ultra SCSI Controller 4 Kbyte SCRIPTS RAM 8 Dword SCRIPTS Prefetch Buffer ROM/Flash Memory Control 944 byte DMA FIFO SCSI SCRIPTS Processor Serial EEPROM Controller and Autoconfiguration Operating Registers SCSI FIFO and SCSI Control Block SE TolerANT Drivers and Receivers Local Memory Bus JTAG JTAG Bus Wide Ultra SCSI Bus ROM/Flash Memory Bus 2-Wire Serial EEPROM Bus 2.
2.1.1.1 Configuration Space The host processor uses the PCI configuration space to initialize the LSI53C875A through a defined set of configuration space registers. The Configuration registers are accessible only by system BIOS during PCI configuration cycles. The configuration space is a contiguous 256 X 8-bit set of addresses. Decoding C_BE[3:0]/ determines if a PCI cycle is intended to access the configuration register space.
Table 2.
2.1.2.3 I/O Read Command The I/O Read command reads data from an agent mapped in I/O address space. All 32 address bits are decoded. 2.1.2.4 I/O Write Command The I/O Write command writes data to an agent mapped in I/O address space. All 32 address bits are decoded. 2.1.2.5 Reserved Command The LSI53C875A does not respond to this command as a slave and it never generates this command as a master. 2.1.2.6 Memory Read Command The Memory Read command reads data from an agent mapped in the Memory Address Space.
2.1.2.10 Memory Read Multiple Command This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C875A supports PCI Memory Read Multiple functionality and issues Memory Read Multiple commands on the PCI bus when the Read Multiple Mode is enabled. This mode is enabled by setting bit 2 (ERMP) of the DMA Mode (DMODE) register.
line. This command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading to a cache line boundary rather than a single memory cycle. The Read Line function in the LSI53C875A takes advantage of the PCI 2.2 specification regarding issuing this command. If the cache mode is disabled, Read Line commands are not issued.
2.1.2.13 Memory Write and Invalidate Command The Memory Write and Invalidate command is identical to the Memory Write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is to say, the master intends to write all bytes within the addressed cache line in a single PCI transaction unless interrupted by the target. This command requires implementation of the PCI Cache Line Size register at address 0x0C in PCI configuration space.
After each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, and no larger than the DMA Mode (DMODE) burst size. The most likely scenario of this scheme is that the chip selects the DMA Mode (DMODE) burst size after alignment, and issues bursts of this size.
software enabled or disabled to allow the user full flexibility in using these commands. 2.1.3.1 Enabling Cache Mode In order to enable the cache logic to issue PCI cache commands (Memory Read Line, Memory Read Multiple, and Memory Write and Invalidate) on any given PCI master operation the following conditions must be met: • The Cache Line Size Enable bit in the DMA Control (DCNTL) register must be set. • The PCI Cache Line Size register must contain a valid binary cache size, i.e.
• To issue Memory Read Multiple commands, the Read Multiple enable bit in the DMA Mode (DMODE) register must be set. • To issue Memory Write and Invalidate commands, both the Write and Invalidate enables in the Chip Test Three (CTEST3) register and the PCI configuration command register must be set. If the corresponding cache command being issued is not enabled then the cache logic falls back to the next command enabled.
• Multiple Memory Write and Invalidates. • A single data residual Memory Write to complete the transfer. Table 2.2 describes PCI cache mode alignment. Table 2.
2.1.3.5 Examples: MR = Memory Read, MRL = Memory Read Line, MRM = Memory Read Multiple, MW = Memory Write, MWI = Memory Write and Invalidate.
C to E: MRM (21 bytes) D to F: MRM (31 bytes) MR (1 byte) A to H: MRM (31 bytes) MRM (32 bytes) MRM (18 bytes) A to G: MRM (31 bytes) MRM (32 bytes) MR (3 bytes) Read Example 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords: A to B: MRL (6 bytes) A to C: MRL (13 bytes) A to D: MRL (17 bytes) C to D: MRL (5 bytes) C to E: MRM (21 bytes) D to F: MRM (32 bytes) A to H: MRM (63 bytes) MRL (16 bytes) MRM (2 bytes) A to G: 2 transfers, MRM (63 bytes), MR (3 bytes) Write Example 1 – Burst
D to F: MW (15 bytes) MWI (16 bytes) MW (1 byte) A to H: MW (15 bytes) MWI (16 bytes) MWI (16 bytes) MWI (16 bytes) MWI (16 bytes) MW (2 bytes) A to G: MW (15 bytes) MWI (16 bytes) MWI (16 bytes) MWI (16 bytes) MW (3 bytes) Write Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords: A to B: MW (6 bytes) A to C: MW (13 bytes) A to D: MW (17 bytes) C to D: MW (5 bytes) C to E: MW (3 bytes) MWI (16 bytes) MW (2 bytes) D to F: MW (15 bytes) MWI (16 bytes) MW (1 byte) A to H: MW (15 bytes)
Write Example 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords: A to B: MW (6 bytes) A to C: MW (13 bytes) A to D: MW (17 bytes) C to D: MW (5 bytes) C to E: MW (21 bytes) D to F: MW (32 bytes) A to H: MW (15 bytes) MWI (64 bytes) MW (2 bytes) A to G: MW (15 bytes) MWI (32 bytes) MW (18 bytes) 2.1.3.6 Memory-to-Memory Moves Memory-to-Memory Moves also support PCI cache commands, as described above, with one limitation.
accessed as a register-oriented device. Error recovery and/or diagnostic procedures use the ability to sample and/or assert any signal on the SCSI bus. In support of SCSI loopback diagnostics, the SCSI core may perform a self-selection and operate as both an initiator and a target. The LSI53C875A is controlled by the integrated SCRIPTS processor through a high-level logical interface. Commands controlling the SCSI core are fetched out of the main host memory or local memory.
The Phase Mismatch Jump logic powers up disabled and must be enabled by setting the Phase Mismatch Jump Enable bit (ENPMJ, bit 7 in the Chip Control 0 (CCNTL0) register). Utilizing the information supplied in the Phase Mismatch Jump Address 1 (PMJAD1) and Phase Mismatch Jump Address 2 (PMJAD2) registers, described in Chapter 4, “Registers,” SCRIPTS handles all overhead involved in a disconnect/reselect sequence with a modest number of instructions. 2.2.
2.2.3 64-Bit Addressing in SCRIPTS The LSI53C875A has a 32-bit PCI interface which provides 64-bit address capability in the initiator mode. DACs can be generated for all SCRIPTS operations. There are six selector registers which hold the upper Dword of a 64-bit address. All but one of these is static and requires manual loading using a CPU access, a Load/Store instruction, or a Memory Move instruction. One of the selector registers is dynamic and is used during 64-bit direct block moves only.
2.2.5 Designing an Ultra SCSI System Since Ultra SCSI is based on existing SCSI standards, it can use existing driver programs as long as the software is able to negotiate for Ultra SCSI synchronous transfer rates. Additional software modifications are needed to take advantage of the new features in the LSI53C875A. For additional information on Ultra SCSI, refer to the SPI-2 working document which is available from the SCSI BBS referenced at the beginning of this manual.
Step 3. Halt the SCSI clock by setting the Halt SCSI Clock bit (SCSI Test Three (STEST3), bit 5). Step 4. Set the clock conversion factor using the SCF and CCF fields in the SCSI Control Three (SCNTL3) register. Step 5. Set the SCLK Quadrupler Select bit (SCSI Test One (STEST1), bit 2). Step 6. Clear the Halt SCSI Clock bit. 2.2.
• On every Store instruction. The Store instruction may also be used to place modified code directly into memory. To avoid inadvertently flushing the prefetch unit contents use the No Flush option for all Store operations that do not modify code within the next 8 Dwords. • On every write to the DMA SCRIPTS Pointer (DSP) register. • On all Transfer Control instructions when the transfer conditions are met.
Load and Store instructions, refer to Chapter 5, “SCSI SCRIPTS Instruction Set.” 2.2.9 JTAG Boundary Scan Testing The LSI53C875A includes support for JTAG boundary scan testing in accordance with the IEEE 1149.1 specification with one exception, which is explained in this section. This device accepts all required boundary scan instructions including the optional CLAMP, HIGH-Z, and IDCODE instructions. The LSI53C875A uses an 8-bit instruction register to support all boundary scan instructions.
2.2.11 Parity Options The LSI53C875A implements a flexible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and has the ability to deliberately send a byte with bad parity over the SCSI bus to test parity error recovery procedures. Table 2.3 defines the bits that are involved in parity control and observation. Table 2.
Table 2.3 Bits Used for Parity Control and Generation Bit Name Location Description Assert SATN/ on Parity Errors SCSI Control Zero (SCNTL0), Bit 1 Causes the LSI53C875A to automatically assert SATN/ when it detects a SCSI parity error while operating as an initiator. Enable Parity Checking SCSI Control Zero (SCNTL0), Bit 3 Enables the LSI53C875A to check for parity errors. The LSI53C875A checks for odd parity.
Table 2.4 SCSI Parity Control EPC1 ASEP2 0 0 Does not check for parity errors. Parity is generated when sending SCSI data. Asserts odd parity when sending SCSI data. 0 1 Does not check for parity errors. Parity is generated when sending SCSI data. Asserts even parity when sending SCSI data. 1 0 Checks for odd parity on SCSI data received. Parity is generated when sending SCSI data. Asserts odd parity when sending SCSI data. 1 1 Checks for odd parity on SCSI data received.
Figure 2.
Figure 2.3 DMA FIFO Sections 8 Bytes Wide .. . .. . 118 Transfers Deep 8 Bits 8 Bits 8 Bits 8 Bits 8 Bits 8 Bits 8 Bits 8 Bits Byte Lane 7 Byte Lane 6 Byte Lane 5 Byte Lane 4 Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0 The LSI53C875A automatically supports misaligned DMA transfers. A 944-byte FIFO allows the LSI53C875A to support 2, 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface. 2.2.12.
Figure 2.
bits of the DBC register from the 10-bit value of the DMA FIFO Byte Offset Counter, which consists of bits [1:0] in the CTEST5 register and bits [7:0] of the DMA FIFO register. AND the result with 0x3FF for a byte count between zero and 944. Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status Two (SSTAT2) registers to determine if any bytes are left in the SCSI Output Data Latch (SODL) register.
then the least significant byte or the most significant byte in the SODR register is full, respectively. Asynchronous SCSI Receive – Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test Five (CTEST5) register cleared), look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC) registers and calculate if there are bytes left in the DMA FIFO. To make this calculation, subtract the seven least significant bits of the DBC register from the 7-bit value of the DFIFO register.
AND the result with 0x3FF for a byte count between zero and 944. Step 2. Read the SCSI Status One (SSTAT1) register and examine bits [7:4], the binary representation of the number of valid bytes in the SCSI FIFO, to determine if any bytes are left in the SCSI FIFO. Step 3. If any wide transfers have been performed using the Chained Move instruction, read the Wide SCSI Receive bit (SCSI Control Two (SCNTL2), bit 0) to determine whether a byte is left in the SCSI Wide Residue (SWIDE) register. 2.2.
Figure 2.5 Regulated Termination for Ultra SCSI UC5601QP (UC5610 for Ultra SCSI) 2.85 V 2 C1 C2 19 REG_OUT DISCONNECT TERML1 TERML2 TERML3 TERML4 TERML5 TERML6 TERML7 TERML8 TERML9 TERML10 TERML11 TERML12 TERML13 TERML14 TERML15 TERML16 TERML17 TERML18 20 21 22 23 24 25 26 27 28 3 4 5 6 7 8 9 10 11 SD0 (J1.40) SD1 (J1.41) SD2 (J1.42) SD3 (J1.43) SD4 (J1.44) SD5 (J1.45) SD6 (J1.46) SD7 (J1.47) SDP0 (J1.48) ATN (J1.55) BSY (J1.57) ACK (J1.58) RST (J1.59) MSG (J1.60) SEL (J1.61) C/D (J1.
situation may occur when a SCSI controller (operating in the initiator mode) tries to select a target and is reselected by another. The Select SCRIPTS instruction has an alternate address to which the SCRIPTS will jump when this situation occurs. The analogous situation for target devices is being selected while trying to perform a reselection.
Figure 2.6 Determining the Synchronous Transfer Rate SCF2 SCF1 SCF0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 1 0 1 SCF Divisor 1 1.5 2 3 3 4 6 8 TP2 Clock Quadrupler TP0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 This point must not exceed 160 MHz SCLK TP1 Divide by 4 SCF Divider Synchronous Divider CCF Divider Asynchronous SCSI Logic QCLK CCF2 0 0 0 1 0 1 1 1 CCF1 0 1 1 0 0 0 1 1 CCF0 1 0 1 0 0 1 0 1 Divisor 1 1.
2.2.15.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0]) The SCF[2:0] bits select the factor by which the frequency of SCLK is divided before being presented to the synchronous SCSI control logic. The output from this divider controls the rate at which data can be received; this rate must not exceed 160 MHz. The receive rate of synchronous SCSI data is one-fourth of the SCF divider output.
• Ultra SCSI Enable bit, SCSI Control Three (SCNTL3) register bit 7. Setting this bit enables Ultra SCSI synchronous transfers in systems that use the internal SCSI clock quadrupler. • TolerANT Enable bit, SCSI Test Three (STEST3) register bit 7. Active negation must be enabled for the LSI53C875A to perform Ultra SCSI transfers. 2.2.16 Interrupt Handling The SCRIPTS processors in the LSI53C875A perform most functions independently of the host microprocessor.
polled when polled interrupts are used. It is also the first register that should be read after the IRQ/ pin is asserted in association with a hardware interrupt. The INTF (Interrupt-on-the-Fly) bit should be the first interrupt serviced. It must be written to one to be cleared. This interrupt must be cleared before servicing any other interrupts. See Register 0x14, Interrupt Status Zero (ISTAT0) register, bit 5 Signal process in Chapter 4, “Registers,” for additional information.
conditions caused the DMA-type interrupt, and clears that DMA interrupt condition. Bit 7 in DSTAT, DFE, is purely a status bit; it will not generate an interrupt under any circumstances and will not be cleared when read. DMA interrupts flush neither the DMA nor SCSI FIFOs before generating the interrupt, so the DFE bit in the DMA Status (DSTAT) register should be checked after any DMA interrupt.
Purpose Timer Expired (GEN), and Handshake-to-Handshake Timer Expired (HTH) interrupts are nonfatal. When operating in the Target mode, CMP, SEL, RSL, Target mode: SATN/ active (M/A), GEN, and HTH are nonfatal. Refer to the description for the Disable Halt on a Parity Error or SATN/ active (Target Mode Only) (DHP) bit in the SCSI Control One (SCNTL1) register to configure the chip’s behavior when the SATN/ interrupt is enabled during Target mode operation.
Interrupts can be disabled by setting SYNC_IRQD bit 0 in the Interrupt Status One (ISTAT1) register. If an interrupt is already asserted and SYNC_IRQD is then set, the interrupt will remain asserted until serviced. At this point, the IRQ/ pin is blocked for future interrupts until this bit is cleared. When the LSI53C875A is initialized, enable all fatal interrupts if you are using hardware interrupts.
generates an interrupt, the bit corresponding to the earlier masked nonfatal interrupt is still set. A related situation to interrupt stacking is when two interrupts occur simultaneously. Since stacking does not occur until the SIP or DIP bits are set, there is a small timing window in which multiple interrupts can occur but are not stacked. These could be multiple SCSI interrupts (SIP set), multiple DMA interrupts (DIP set), or multiple SCSI and multiple DMA interrupts (both SIP and DIP set).
• If the instruction is a JUMP/CALL WHEN/IF , the DMA SCRIPTS Pointer (DSP) is updated to the transfer address before halting. • All other instructions may halt before completion. 2.2.16.7 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C875A. It can be repeated during polling or should be called when the IRQ/ pin is asserted during hardware interrupts. 1. Read Interrupt Status Zero (ISTAT0). 2.
2.2.17 Chained Block Moves Since the LSI53C875A has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI Send (WSS) and Wide SCSI Receive (WSR) bits in the SCSI Control Two (SCNTL2) register are used to facilitate these situations. The Chained Block Move instruction is illustrated in Figure 2.7.
Figure 2.7 Block Move and Chained Block Move Instructions Host Memory SCSI Bus 0x03 0x02 0x01 0x00 0x04 0x03 0x07 0x06 0x05 0x04 0x06 0x05 0x0B 0x0A 0x09 0x08 0x0F 0x0E 0x0D 0x0C 0x13 0x12 0x11 0x10 0x09 0x07 0x0B 0x0A 0x0D 0x0C 32 Bits 16 Bits 2.2.17.
two bytes are sent out across the bus, regardless of the type of Block Move instruction (normal or chained). The flag is automatically cleared when the “married” word is sent. The flag is alternately cleared through SCRIPTS or by the microprocessor. Also, the microprocessor or SCRIPTS can use this bit for error detection and recovery purposes. 2.2.17.
2.2.17.5 Chained Block Move SCRIPTS Instruction A chained Block Move SCRIPTS instruction is primarily used to transfer consecutive data send or data receive blocks. Using the chained Block Move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. Behavior of the chained Block Move instruction varies slightly for sending and receiving data.
send command, the first byte of the data send command is assumed to be the high-order byte and is “married” with the low-order byte stored in the lower byte of the SCSI Output Data Latch (SODL) register before the two bytes are sent across the SCSI bus. For “N” consecutive wide data send Block Move commands, the first through the (Nth – 1) Block Move instructions should be Chained Block Moves. CHMOV 5, 3 when Data_Out Moves five bytes from address 0x03 in the host memory to the SCSI bus.
The LSI53C875A supports a variety of sizes and speeds of expansion ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of pins MAD[3:1] allows the user to define how much external memory is available to the LSI53C875A. Table 2.6 shows the memory space associated with the possible values of MAD[3:1]. The MAD[3:1] pins are fully described in Chapter 3, “Signal Descriptions.” Table 2.
2.4 Serial EEPROM Interface The LSI53C875A implements an interface that allows attachment of a serial EEPROM device to the GPIO0 and GPIO1 pins. There are two modes of operation relating to the serial EEPROM and the Subsystem ID and Subsystem Vendor ID registers. These modes are programmable through the MAD7 pin which is sampled at power-up. 2.4.1 Default Download Mode In this mode, MAD7 is pulled down internally, GPIO0 is the serial data signal (SDA) and GPIO1 is the serial clock signal (SCL).
Table 2.7 Mode A Serial EEPROM Data Format Byte Name 0xFB SVID(0) Subsystem Vendor ID, LSB. This byte is loaded into the least significant byte of the Subsystem Vendor ID register in the appropriate PCI configuration space at chip power-up. 0xFC SVID(1) Subsystem Vendor ID, MSB. This byte is loaded into the most significant byte of the Subsystem Vendor ID register in the appropriate PCI configuration space at chip power-up. 0xFD SID(0) Subsystem ID, LSB.
The LSI53C875A power states shown in Table 2.8 are independently controlled through two power state bits that are located in the PCI Power Management Control/Status (PMCSR) register 0x44. Table 2.
2.5.3 Power State D2 Power state D2 is a lower power state than D1. In this state the LSI53C875A core is placed in the coma mode. The following PCI Configuration Space command register enable bits are suppressed: • I/O Space Enable • Memory Space Enable • Bus Mastering Enable • SERR/Enable • Enable Parity Error Response Thus, the memory and I/O spaces cannot be accessed, and the LSI53C875A cannot be a PCI bus master. Furthermore, all interrupts are disabled when in power state D2.
2-54 Functional Description
Chapter 3 Signal Descriptions This chapter presents the LSI53C875A pin configuration and signal definitions using tables and illustrations. This chapter contains the following sections: • Section 3.1, “LSI53C875A Functional Signal Grouping” • Section 3.2, “Signal Descriptions” • Section 3.3, “PCI Bus Interface Signals” • Section 3.4, “SCSI Bus Interface Signals” • Section 3.5, “GPIO Signals” • Section 3.6, “ROM Flash and Memory Interface Signals” • Section 3.
3.1 LSI53C875A Functional Signal Grouping Figure 3.1 presents the LSI53C875A signals by functional group. Figure 3.
3.2 Signal Descriptions The Signal Descriptions are divided into PCI Bus Interface Signals, SCSI Bus Interface Signals, GPIO Signals, ROM Flash and Memory Interface Signals, Test Interface Signals, and Power and Ground Signals. The PCI Bus Interface Signals are subdivided into System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, Error Reporting Signals, and Interrupt Signal.
3.3 PCI Bus Interface Signals The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, Error Reporting Signals, and Interrupt Signal. 3.3.1 System Signals Table 3.2 describes the System signals. Table 3.2 System Signals Name PQFP BGA CLK 145 A6 I N/A Clock provides timing for all transactions on the PCI bus and is an input to every PCI device.
3.3.2 Address and Data Signals Table 3.3 describes Address and Data signals. Table 3.3 Address and Data Signals Name PQFP BGA Type Strength Description AD[31:0] 150, 151, 153, 154, 156, 157, 159, 160, 3, 5, 6, 7, 9, 11–13, 28– 30, 32, 34– 36, 38, 40, 41, 43, 44, 46, 47, 49, 50 B5, C5, A4, B4, A3, C4, D4, A2, C2, E5, C1, D3, E4-E1, H5, J1, J2, H6, K2, J4, L1, L2, M1, N1, M3, L3, N3, L4, K5, N4 T/S 8 mA PCI Physical Dword Address and Data are multiplexed on the same PCI pins.
3.3.3 Interface Control Signals Table 3.4 describes the Interface Control signals. Table 3.4 Interface Control Signals Name PQFP BGA Type FRAME/ 16 F2 S/T/S 8 mA PCI Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME/ is asserted to indicate that a bus transaction is beginning. While FRAME/ is deasserted, either the transaction is in the final data phase or the bus is idle.
3.3.4 Arbitration Signals Table 3.5 describes Arbitration signals. Table 3.5 Arbitration Signals Name PQFP BGA Type Strength Description REQ/ 148 E6 O GNT/ 147 D6 I 8 mA PCI Request indicates to the system arbiter that this agent desires use of the PCI bus. This is a point-to-point signal. Every master has its own REQ/ signal. N/A Grant indicates to the agent that access to the PCI bus has been granted. This is a point-to-point signal. Every master has its own GNT/ signal. 3.3.
3.3.6 Interrupt Signal Table 3.7 describes the Interrupt signal. Table 3.7 Interrupt Signal Name PQFP BGA IRQ/ 52 M5 Type O Strength Description 8 mA PCI Interrupt Request. This signal, when asserted LOW, indicates that an interrupting condition has occurred and that service is required from the host CPU. The output drive of this pin is open drain. 1. See Register 0x4D, SCSI Test One (STEST1) in Chapter 4 for additional information on this signal. 3.
3.4.2 SCSI Signals Table 3.9 describes the SCSI signals. Table 3.9 SCSI Signals Name PQFP BGA SD[15:0] 113, 115–17, 85–87, 89, 102, 103, 105–108, 110, 111 D13, E10, C13, D11, J9, L13, K11, J10, G10, G9, F13, F11–9, E12, E11 I/O 48 mA SCSI SCSI Data. F8, G13 I/O 48 mA SCSI SCSI Parity. SDP[1:0] 112, 101 Type Strength Description 3.4.3 SCSI Control Signals Table 3.10 describes the SCSI Control signals. Table 3.
3.5 GPIO Signals Table 3.11 describes the SCSI GPIO signals. Table 3.11 GPIO Signals Name PQFP BGA Type Strength Description GPIO0_FETCH/ 53 N5 I/O 8 mA SCSI General Purpose I/O pin. Optionally, when driven LOW, indicates that the next bus request will be for an opcode fetch. This pin is programmable at power-up through the MAD7 pin to serve as the data signal for the serial EEPROM interface. This signal can also be programmed to be driven LOW when the LSI53C875A is active on the SCSI bus.
3.6 ROM Flash and Memory Interface Signals Table 3.12 describes the ROM Flash and Memory Interface signals. Table 3.12 ROM Flash and Memory Interface Signals Name PQFP BGA Type Strength Description MWE/ 139 C7 O 4 mA Memory Write Enable. This pin is used as a write enable signal to an external flash memory. MCE/ 141 A7 O 4 mA Memory Chip Enable. This pin is used as a chip enable signal to an external EEPROM or flash memory device. MOE/ 140 B7 O 4 mA Memory Output Enable.
Table 3.12 ROM Flash and Memory Interface Signals (Cont.) Name PQFP BGA MAD[7:0] 59–62, 64–67 L7, M7, N7, K7, M8, N8, L8, K8 Type Strength Description I/O 4 mA Memory Address/Data Bus. This bus is used in conjunction with the memory address strobe pins and external address latches to assemble up to a 20-bit address for an external EEPROM or flash memory. This bus will put out the least significant byte first and finishes with the most significant bits.
3.8 Power and Ground Signals Table 3.14 describes the Power and Ground signals. Table 3.14 Power and Ground Signals Name PQFP BGA Type Strength Description VSS_I/O 4, 10, 14, 18, 23, 27, 31, 37, 42, 48, 69, 79, 88, 93, 99, 104, 109, 114, 123, 133, 152, 158 A9, B11, D12, E13, F12, G11, J13, K10, K12, N9 G N/A Ground for PCI bus drivers/receivers, SCSI bus drivers/receivers, local memory interface drivers, and other I/O pins.
3.9 MAD Bus Programming The MAD[7:0] pins, in addition to serving as the address/data bus for the local memory interface, also are used to program power-up options for the chip. A particular option is programmed allowing the internal pull-down current sink to pull the pin LOW at reset or by connecting a 4.7 kΩ resistor between the appropriate MAD[x] pin and VSS. The pull-down resistors require that HC or HCT external components are used for the memory interface.
• The MAD[0] pin is the slow ROM pin. When pulled up, it enables two extra cycles of data access time to allow use of slower memory devices. • All MAD pins have internal pull-down resistors.
3-16 Signal Descriptions
Chapter 4 Registers This chapter describes all LSI53C875A registers and is divided into the following sections: • Section 4.1 “PCI Configuration Registers” • Section 4.2 “SCSI Registers” • Section 4.3 “64-Bit SCRIPTS Selectors” • Section 4.4 “Phase Mismatch Jump Registers” In the register descriptions, the term “set” is used to refer to bits that are programmed to a binary one. Similarly, the term “cleared” is used to refer to bits that are programmed to a binary zero.
bits that are currently supported by the LSI53C875A are described in this chapter. Reserved bits should not be accessed. Table 4.
Registers: 0x02–0x03 Device ID Read Only 15 0 DID 0 0 0 0 DID 0 0 0 0 0 0 0 1 0 0 1 1 Device ID [15:0] This 16-bit register identifies the particular device. The LSI53C875A Device ID is 0x0013. Registers: 0x04–0x05 Command Read/Write 15 9 R x x x x x x x 8 7 6 5 4 3 2 1 0 SE R EPER R WIE R EBM EMS EIS 0 x 0 x 0 x 0 0 0 The Command register provides coarse control over a device’s ability to generate and respond to PCI cycles.
4-4 5 R Reserved WIE Write and Invalidate Enable 4 This bit allows the LSI53C875A to generate write and invalidate commands on the PCI bus. The WIE bit in the DMA Control (DCNTL) register must also be set for the device to generate Write and Invalidate commands. R Reserved EBM Enable Bus Mastering 2 This bit controls the ability of the LSI53C875A to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses.
Registers: 0x06–0x07 Status Read/Write 15 14 13 12 DPE SSE RMA RTA 0 0 0 11 10 R DT[1:0] x 0 0 9 8 7 DPR 1 0 5 R x x 4 3 0 NC x 1 R x x x x Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set. A bit is cleared whenever the register is written, and the data in the corresponding bit location is a one. For instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register.
These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSI53C875A supports a value of 0b01. DPR Data Parity Error Reported 8 This bit is set when all of the following conditions are met: • The bus agent asserted PERR/ itself or observed PERR/ asserted. • The agent setting this bit acted as the bus master for the operation in which the error occurred.
Registers: 0x09–0x0B Class Code Read Only 23 0 CC 0 0 0 0 0 0 0 1 0 CC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Class Code [23:0] This 24-bit register is used to identify the generic function of the device. The upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identifies a specific register level programming interface. The value of this register is 0x010000, which identifies a SCSI controller.
Register: 0x0D Latency Timer Read/Write 7 0 LT 0 0 LT 0 0 0 0 0 0 Latency Timer [7:0] The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. The LSI53C875A supports this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the LSI53C875A.
Registers: 0x10–0x13 Base Address Register Zero (I/O) Read/Write 31 0 BAR0 0 0 0 0 0 0 0 0 0 0 0 0 BAR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Base Address Register Zero - I/O [31:0] This base address register is used to map the operating register set into I/O space. The LSI53C875A requires 256 bytes of I/O space for this base address register. It has bit zero hardwired to one.
Registers: 0x18–0x1B Base Address Register Two (SCRIPTS RAM) Read/Write 31 0 BAR2 0 0 0 0 0 0 0 0 0 0 0 0 BAR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Base Address Register Two [31:0] This base register is used to map the SCRIPTS RAM into memory space. The default value of this register is 0x00000000. The LSI53C875A points to 4096 bytes of address space with this register. This register has bits [11:0] hardwired to 0b000000000000.
controller installed on them (and therefore the same Vendor ID and Device ID). If the external serial EEPROM interface is enabled (MAD[7] LOW), this register is automatically loaded at power-up from the external serial EEPROM and will contain the value downloaded from the serial EEPROM or a value of 0x0000 if the download fails. If the external serial EEPROM interface is disabled (MAD[7] HIGH), this register returns a value of 0x1000 (LSI Logic Vendor ID).
value that should be stored in the external serial EEPROM is vendor specific. Please see the Section 2.4 “Serial EEPROM Interface” in Chapter 2 for additional information on downloading a value for this register.
Register: 0x34 Capabilities Pointer Read Only 7 0 CP 0 1 CP 0 0 0 0 0 0 Capabilities Pointer [7:0] This register indicates that the first extended capability register is located at offset 0x40 in the PCI Configuration. Registers: 0x35–0x3B Reserved Register: 0x3C Interrupt Line Read/Write 7 0 IL 0 IL 0 0 0 0 0 0 0 Interrupt Line [7:0] This register is used to communicate interrupt line routing information.
Register: 0x3D Interrupt Pin Read Only 7 0 IP 0 0 IP 0 0 0 0 0 1 Interrupt Pin [7:0] This register indicates which interrupt pin the device uses. Its value is set to 0x01 for the INTA/ signal. Register: 0x3E Min_Gnt Read Only 7 0 MG 0 0 MG 0 1 0 0 0 1 MIN_GNT [7:0] This register is used to specify the desired settings for latency timer values. Min_Gnt is used to specify how long a burst period the device needs. The value specified in this register is in units of 0.25 microseconds.
Register: 0x40 Capability ID Read Only 7 0 CID 0 0 CID 0 0 0 0 0 1 Cap_ID [7:0] This register indicates the type of data structure currently being used. It is set to 0x01, indicating the Power Management Data Structure. Register: 0x41 Next Item Pointer Read Only 7 0 NIP 0 0 NIP 0 0 0 0 0 0 Next_Item_Ptr [7:0] Bits [7:0] contain the offset location of the next item in the controller’s capabilities list.
D2S D2_Support 10 The LSI53C875A sets this bit to indicate support for power management state D2. D1S D1_Support The LSI53C875A sets this bit to indicate support for power management state D1. R Reserved DSI Device Specific Initialization 5 This bit is cleared to indicate that the LSI53C875A requires no special initialization before the generic class device driver is able to use it.
DSCL Data_Scale [14:13] The LSI53C875A does not support the data register. Therefore, these two bits are always cleared. DSLT Data_Select [12:9] The LSI53C875A does not support the data register. Therefore, these four bits are always cleared. PEN PME_Enable The LSI53C875A always returns a zero for this bit to indicate that PME assertion is disabled. R Reserved PWS[1:0] Power State [1:0] Bits [1:0] are used to determine the current power state of the LSI53C875A.
Register: 0x47 Data Read Only 7 0 DATA 0 DATA 0 0 0 0 0 0 0 Data [7:0] This register provides an optional mechanism for the function to report state-dependent operating data. The LSI53C875A does not use this register and always returns 0x00. 4.2 SCSI Registers The control registers for the SCSI core are directly accessible from the PCI bus using Memory or I/O mapping. The address map of the SCSI registers is shown in Table 4.2.
Table 4.
Register: 0x00 SCSI Control Zero (SCNTL0) Read/Write 7 6 ARB[1:0] 1 ARB[1:0] 5 4 3 2 1 0 START WATN EPC R AAP TRG 0 0 0 x 0 0 1 Arbitration Mode Bits 1 and 0 ARB1 ARB0 Arbitration Mode 0 0 Simple arbitration 0 1 Reserved 1 0 Reserved 1 1 Full arbitration, selection/reselection [7:6] Simple Arbitration 1. The LSI53C875A waits for a bus free condition to occur. 2. It asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) register) onto the SCSI bus.
Full Arbitration, Selection/Reselection 1. The LSI53C875A waits for a bus free condition. 2. It asserts SBSY/ and its SCSI ID (the highest priority ID stored in the SCSI Chip ID (SCID) register) onto the SCSI bus. 3. If the SSEL/ signal is asserted by another SCSI device or if the LSI53C875A detects a higher priority ID, the LSI53C875A deasserts SBSY, deasserts its ID, and waits until the next bus free state to try arbitration again. 4.
WATN Select with SATN/ on a Start Sequence 4 When this bit is set and the LSI53C875A is in the initiator mode, the SATN/ signal is asserted during selection of a SCSI target device. This is to inform the target that the LSI53C875A has a message to send. If a selection time-out occurs while attempting to select a target device, SATN/ is deasserted at the same time SSEL/ is deasserted. When this bit is cleared, the SATN/ signal is not asserted during selection.
(SET TARGET or CLEAR TARGET). When this bit is set, the chip is a target device by default. When this bit is cleared, the LSI53C875A is an initiator device by default. Caution: Writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes.
may transfer up to three additional bytes before halting to synchronize between internal core cells. During synchronous operation, the LSI53C875A transfers data until there are no outstanding synchronous offsets. If the LSI53C875A is receiving data, any data residing in the DMA FIFO is sent to memory before halting. When this bit is set, the LSI53C875A does not halt the SCSI transfer when SATN/ or a parity error is received.
SCSI Control Zero (SCNTL0) register are set for full arbitration and selection before setting this bit. Arbitration is retried until won. At that point, the LSI53C875A holds SBSY and SSEL asserted, and waits for a select or reselect sequence. The Immediate Arbitration bit is cleared automatically when the selection or reselection sequence is completed, or times out. An unexpected disconnect condition clears IARB with it attempting arbitration.
Caution: Writing to this register while not connected may cause the loss of a selection/reselection by clearing the Connected bit. Register: 0x02 SCSI Control Two (SCNTL2) Read/Write 7 6 5 4 3 2 1 0 SDU CHM SLPMD SLPHBEN WSS VUE0 VUE1 WSR 0 0 0 0 0 0 0 0 SDU SCSI Disconnect Unexpected 7 This bit is valid in the initiator mode only. When this bit is set, the SCSI core is not expecting the SCSI bus to enter the Bus Free phase.
combined with the first byte from the subsequent transfer so that a wide transfer is completed. SLPMD SLPAR Mode 5 If this bit is cleared, the SCSI Longitudinal Parity (SLPAR) register functions as a byte-wide longitudinal parity register. If this bit is set, the SLPAR functions as a word-wide longitudinal parity function. The high or low byte of the SLPAR word is accessible through the SLPAR register. Which byte is accessible is controlled by the SLPHBEN bit.
group codes. If this bit is set, the device does not reload the Block Move byte count, regardless of the group code. WSR Wide SCSI Receive 0 When read, this bit returns the value of the Wide SCSI Receive (WSR) flag. Setting this bit clears the WSR flag. This clearing function is self-clearing.
SCF[2:0] Synchronous Clock Conversion Factor [6:4] These bits select a factor by which the frequency of SCLK is divided before being presented to the synchronous SCSI control logic. Write these to the same value as the Clock Conversion Factor bits below unless fast SCSI operation is desired. See the SCSI Transfer (SXFER) register description for examples of how the SCF bits are used to calculate synchronous transfer periods.
Register: 0x04 SCSI Chip ID (SCID) Read/Write 7 6 5 4 R RRE SRE R x 0 0 x 3 0 ENC 0 0 0 R Reserved 7 RRE Enable Response to Reselection 6 When this bit is set, the LSI53C875A is enabled to respond to bus-initiated reselection at the chip ID in the Response ID Zero (RESPID0) and Response ID One (RESPID1) registers. Note that the chip does not automatically reconfigure itself to the initiator mode as a result of being reselected.
Register: 0x05 SCSI Transfer (SXFER) Read/Write 7 5 4 0 TP[2:0] 0 Note: MO[4:0] 0 0 0 0 0 0 0 When using Table Indirect I/O commands, bits [7:0] of this register are loaded from the I/O data structure. TP[2:0] SCSI Synchronous Transfer Period [7:5] These bits determine the SCSI synchronous transfer period used by the LSI53C875A when sending synchronous SCSI data in either the initiator or target mode. These bits control the programmable dividers in the chip.
(This SCSI synchronous core clock is determined in SCNTL3 bits [6:4], ExtCC = 1 if SCNTL1 bit 7 is asserted and the LSI53C875A is sending data. ExtCC = 0 if the LSI53C875A is receiving data.) SXFERP = 100 ÷ 25 = 4 Where: SXFERP Synchronous transfer period. SSCP SCSI synchronous core period. SSCF SCSI synchronous core frequency. ExtCC Extra clock cycle of data setup. Table 4.3 shows examples of synchronous transfer periods and rates for SCSI-1. Table 4.
Table 4.4 shows example transfer periods and rates for fast SCSI-2 and Ultra SCSI. Table 4.4 Example Transfer Periods and Rates for Fast SCSI-2 and Ultra SCSI CLK (MHz) SCSI CLK ÷ SCNTL3 Bits [6:4] 1601 1 XFERP Synch. Transfer Period (ns) Synch. Transfer Rate (Mbytes/s) 2 4 50 20 4 4 100 10 80 1 4 50 20 50 1 4 80 12.5 50 1 5 100 10.0 40 1 4 100 10.0 37.50 1 4 106.67 9.375 33.33 1 4 120 8.33 25 1 4 160 6.25 20 1 4 200 5 16.67 1 4 240 4.17 160 1.
Table 4.
Register: 0x06 SCSI Destination ID (SDID) Read/Write 7 4 3 0 R x ENC x x x 0 0 0 0 R Reserved [7:4] ENC Encoded Destination SCSI ID [3:0] Writing these bits set the SCSI ID of the intended initiator or target during SCSI reselection or selection phases, respectively. When executing SCRIPTS, the SCRIPTS processor writes the destination SCSI ID to this register. The SCSI ID is defined by the user in a SCRIPTS Select or Reselect instruction. The value written is the binary-encoded ID.
is also possible to program these signals as live inputs and sense them through a SCRIPTS register to register Move Instruction. GPIO4 may be used to enable or disable VPP, the 12 Volt power supply to the external flash memory. This bit powers up with the power to external memory disabled. GPIO[3:0] default as inputs and GPIO4 defaults as an output pin. When configured as inputs, an internal pull-down is enabled for GPIO[4:2]. For GPIO[1:0], internal pull-ups are enabled.
a byte stored in system memory, the byte must first be moved to an intermediate LSI53C875A register (such as a SCRATCH register), and then to the SFBR. This register also contains the state of the lower eight bits of the SCSI data bus during the Selection phase if the COM bit in the DMA Control (DCNTL) register is clear. If the COM bit is cleared, do not access this register using SCRIPTS operations, as nondeterminate operations may occur.
Register: 0x0A SCSI Selector ID (SSID) Read Only 7 6 4 0 R VAL 0 3 x x ENID x 0 0 0 0 VAL SCSI Valid 7 If VAL is asserted, then the two SCSI IDs are detected on the bus during a bus-initiated selection or reselection, and the encoded destination SCSI ID bits below are valid. If VAL is deasserted, only one ID is present and the contents of the encoded destination ID are meaningless.
REQ SREQ/ Status 7 ACK SACK/ Status 6 BSY SBSY/ Status 5 SEL SSEL/ Status 4 ATN SATN/ Status 3 MSG SMSG/ Status 2 C_D SC_D/ Status 1 I_O SI_O/ Status 0 Register: 0x0C DMA Status (DSTAT) Read Only 7 6 5 4 3 2 1 0 DFE MDPE BF ABRT SSI SIR R IID 1 0 0 0 0 0 x 0 Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C875A stacks interrupts)
MDPE Master Data Parity Error 6 This bit is set when the LSI53C875A as a master detects a data parity error, or a target device signals a parity error during a data phase. This bit is completely disabled by the Master Parity Error Enable bit (bit 3 of Chip Test Four (CTEST4)). BF Bus Fault 5 This bit is set when a PCI bus fault condition is detected. A PCI bus fault can only occur when the LSI53C875A is bus master, and is defined as a cycle that ends with a Bad Address or Target Abort Condition.
• During a Transfer Control instruction, the Compare Data (bit 18) and Compare Phase (bit 17) bits are set in the DMA Byte Counter (DBC) register while the LSI53C875A is in target mode. • During a Transfer Control instruction, the Carry Test bit (bit 21) is set and either the Compare Data (bit 18) or Compare Phase (bit 17) bit is set. • A Transfer Control instruction is executed with the reserved bit 22 set.
Register: 0x0D SCSI Status Zero (SSTAT0) Read Only 4-42 7 6 5 4 3 2 1 0 ILF ORF OLF AIP LOA WOA RST SDP0 0 0 0 0 0 0 0 0 ILF SIDL Least Significant Byte Full 7 This bit is set when the least significant byte in the SCSI Input Data Latch (SIDL) register contains data. Data is transferred from the SCSI bus to the SCSI Input Data Latch register before being sent to the DMA FIFO and then to the host bus. The SIDL register contains SCSI data received asynchronously.
AIP Arbitration in Progress 4 Arbitration in Progress (AIP = 1) indicates that the LSI53C875A has detected a Bus Free condition, asserted SBSY, and asserted its SCSI ID onto the SCSI bus. LOA Lost Arbitration 3 When set, LOA indicates that the LSI53C875A has detected a bus free condition, arbitrated for the SCSI bus, and lost arbitration due to another SCSI device asserting the SSEL/ signal.
synchronous data transfers, or up to 31 words for wide. Values over 31 will not occur. Table 4.
Table 4.6 SCSI Synchronous Data FIFO Word Count (Cont.
Register: 0x0F SCSI Status Two (SSTAT2) Read Only 4-46 7 6 5 4 3 2 1 0 ILF1 ORF1 OLF1 FF4 SPL1 R LDSC SDP1 0 0 0 0 x x 1 x ILF1 SIDL Most Significant Byte Full 7 This bit is set when the most significant byte in the SCSI Input Data Latch (SIDL) contains data. Data is transferred from the SCSI bus to the SCSI Input Data Latch register before being sent to the DMA FIFO and then to the host bus. The SIDL register contains SCSI data received asynchronously.
field, see the definition for SCSI Status One (SSTAT1) bits [7:4]. SPL1 Latched SCSI Parity for SD[15:8] 3 This active HIGH bit reflects the SCSI odd parity signal corresponding to the data latched into the most significant byte in the SCSI Input Data Latch (SIDL) register. R Reserved LDSC Last Disconnect 1 This bit is used in conjunction with the Connected (CON) bit in SCSI Control One (SCNTL1).
Register: 0x14 Interrupt Status Zero (ISTAT0) Read/Write 7 6 5 4 3 2 1 0 ABRT SRST SIGP SEM CON INTF SIP DIP 0 0 0 0 0 0 0 0 This register is accessible by the host CPU while a LSI53C875A is executing SCRIPTS (without interfering in the operation of the function). It is used to poll for interrupts if hardware interrupts are disabled. Read this register after servicing an interrupt to check for stacked interrupts.
clear the ID Mode bit or any of the PCI configuration registers. This bit is not self-clearing; it must be cleared to clear the reset condition (a hardware reset also clears this bit). SIGP Signal Process 5 SIGP is a R/W bit that is writable at any time, and polled and reset using Chip Test Two (CTEST2). The SIGP bit is used in various ways to pass a flag to or from a running SCRIPTS instruction. The only SCRIPTS instruction directly affected by the SIGP bit is Wait for Selection/Reselection.
the SCRIPTS processor is still executing a SCRIPTS program. If this bit is set when the Interrupt Status Zero (ISTAT0) or Interrupt Status One (ISTAT1) registers are read they are not automatically cleared. To clear this bit, write it to a one. The reset operation is self-clearing. Note: If the INTF bit is set but SIP or DIP are not set, do not attempt to read the other chip status registers. An Interrupt-on-the-Fly interrupt must be cleared before servicing any other interrupts indicated by SIP or DIP.
• A bus fault is detected • An abort condition is detected • A SCRIPTS instruction is executed in single step mode • A SCRIPTS interrupt instruction is executed • An illegal instruction is detected To determine exactly which condition(s) caused the interrupt, read the DMA Status (DSTAT) register.
addition, this bit may be read and written while SCRIPTS are executing. Register: 0x16 Mailbox Zero (MBOX0) Read/Write 7 0 MBOX0 0 0 MBOX0 Note: 0 0 0 0 0 0 Mailbox Zero [7:0] These are general purpose bits that may be read or written while SCRIPTS are running. They also may be read or written by the SCRIPTS processor. The host and the SCRIPTS processor code could potentially attempt to access the same mailbox byte at the same time.
Register: 0x18 Chip Test Zero (CTEST0) Read/Write 7 0 FMT 1 1 FMT 1 1 1 1 1 1 Byte Empty in DMA FIFO [7:0] These bits identify the bottom bytes in the DMA FIFO that are empty. Each bit corresponds to a byte lane in the DMA FIFO. For example, if byte lane three is empty, then FMT3 will be set. Since the FMT flags indicate the status of bytes at the bottom of the FIFO, if all FMT bits are set, the DMA FIFO is empty.
Register: 0x1A Chip Test Two (CTEST2) Read Only (bit 3 write) 7 6 5 4 3 2 1 0 DDIR SIGP CIO CM PCICIE TEOP DREQ DACK 0 0 x x 0 0 0 1 DDIR Data Transfer Direction 7 This status bit indicates which direction data is being transferred. When this bit is set, the data is transferred from the SCSI bus to the host bus. When this bit is clear, the data is transferred from the host bus to the SCSI bus.
Base Address Register One (MEMORY). This is the memory mapped operating register base address. Bits [9:0] will be 0. The SCRATCHB register contains bits [31:13] of the RAM Base Address value from the PCI Base Address Register Two (SCRIPTS RAM). This is the base address for the internal 4 Kbytes RAM. Bits [11:0] will be 0. Bits [23:16] of SCRIPTS Fetch Selector (SFS) contain the PCI Revision ID (Rev ID) register value and bits [15:0] contain the PCI Device ID register value.
Register: 0x1B Chip Test Three (CTEST3) Read/Write 7 4 V x x x x 3 2 1 0 FLF CLF FM WRIE 0 0 0 0 V Chip Revision Level [7:4] These bits identify the chip revision level for software purposes. It should have the same value as the lower nibble of the PCI Revision ID (Rev ID) register, at address 0x08 in the configuration space.
WRIE Write and Invalidate Enable 0 This bit, when set, causes the issuing of Write and Invalidate commands on the PCI bus whenever legal. The Write and Invalidate Enable bit in the PCI Configuration Command register must also be set in order for the chip to generate Write and Invalidate commands.
while data is being transferred between the two cores. Once the chip has stopped transferring data, these bits are stable. The DMA FIFO (DFIFO) register counts the number of bytes transferred between the DMA core and the SCSI core. The DMA Byte Counter (DBC) register counts the number of bytes transferred across the host bus. The difference between these two counters represents the number of bytes remaining in the DMA FIFO.
Register: 0x21 Chip Test Four (CTEST4) Read/Write 7 6 5 4 3 BDIS FBL3 ZSD SRTM MPEE 0 0 0 0 0 2 0 FBL[2:0] 0 0 0 BDIS Burst Disable 7 When set, this bit causes the LSI53C875A to perform back-to-back cycles for all transfers. When this bit is cleared, back-to-back transfers for opcode fetches and burst transfers for data moves are performed. FBL3 FIFO Byte Control 6 This bit is used with FBL[2:0]. See Bits [2:0] description in this register.
LSI53C875A is informed of the error by the PERR/ pin being asserted by the target. When this bit is cleared, the LSI53C875A does not interrupt if a master parity error occurs. This bit is cleared at power-up.
the current DBC value. This bit automatically clears itself after incrementing the DNAD register. BBCK Clock Byte Counter 6 Setting this bit decrements the byte count contained in the 24-bit DBC register. It is decremented based on the DMA Byte Counter (DBC) contents and the current DMA Next Address (DNAD) value. This bit automatically clears itself after decrementing the DBC register. DFS DMA FIFO Size 5 This bit controls the size of the DMA FIFO. When clear, the DMA FIFO appears as only 112 bytes deep.
BO[9:8] DMA FIFO Byte Offset Counter, Bits [9:8] [1:0] These are the upper two bits of the DFBOC. The DFBOC consists of these bits, and the DMA FIFO (DFIFO) register, bits [7:0]. Register: 0x23 Chip Test Six (CTEST6) Read/Write 7 0 DF 0 0 DF 0 0 0 0 0 0 DMA FIFO [7:0] Writing to this register writes data to the appropriate byte lane of the DMA FIFO as determined by the FBL bits in the Chip Test Four (CTEST4) register.
LSI53C875A. The DBC counter is decremented each time data is transferred on the PCI bus. It is decremented by an amount equal to the number of bytes that are transferred. The maximum number of bytes that can be transferred in any one Block Move command is 16,777,215 bytes. The maximum value that can be loaded into the DMA Byte Counter (DBC) register is 0xFFFFFF.
Registers: 0x28–0x2B DMA Next Address (DNAD) Read/Write 31 0 DNAD 0 0 0 0 0 0 0 0 0 0 0 0 DNAD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA Next Address [31:0] This 32-bit register contains the general purpose address pointer. At the start of some SCRIPTS operations, its value is copied from the DMA SCRIPTS Pointer Save (DSPS) register. Its value may not be valid except in certain abort conditions. The default value of this register is zero.
Registers: 0x30–0x33 DMA SCRIPTS Pointer Save (DSPS) Read/Write 31 0 DSPS x x x x x x x x x x x x DSPS x x x x x x x x x x x x x x x x x x x x DMA SCRIPTS Pointer Save [31:0] This register contains the second Dword of a SCRIPTS instruction. It is overwritten each time a SCRIPTS instruction is fetched. When a SCRIPTS interrupt instruction is executed, this register holds the interrupt vector. The power-up value of this register is indeterminate.
Register: 0x38 DMA Mode (DMODE) Read/Write 7 6 BL[1:0] 0 BL[1:0] 0 5 4 3 2 1 0 SIOM DIOM ERL ERMP BOF MAN 0 0 0 0 0 0 Burst Length [7:6] These bits control the maximum number of Dwords transferred per bus ownership, regardless of whether the transfers are back-to-back, burst, or a combination of both. The LSI53C875A asserts the Bus Request (REQ/) output when the DMA FIFO can accommodate a transfer of at least one burst threshold of data.
BL2 (CTEST5 bit 2) BL1 BL0 Burst Length Transfers Dwords 0 0 0 2 4 0 0 1 4 8 0 1 0 8 16 0 1 1 16 321 1 0 0 32 641 1 0 1 64 1281 1 1 0 64 1281 1 1 1 Reserved Reserved 1. The 944-byte FIFO must be enabled for these burst sizes. SIOM Source I/O Memory Enable 5 This bit is defined as an I/O Memory Enable bit for the source address of a Memory Move or Block Move Command.
4-68 ERMP Enable Read Multiple 2 If this bit is set and cache mode is enabled, a Read Multiple command is used on all read cycles when it is legal. BOF Burst Opcode Fetch Enable 1 Setting this bit causes the LSI53C875A to fetch instructions in burst mode. Specifically, the chip bursts in the first two Dwords of all instructions using a single bus ownership. If the instruction is a Memory-to-Memory Move type, the third Dword is accessed in a subsequent bus ownership.
Register: 0x39 DMA Interrupt Enable (DIEN) Read/Write 7 6 5 4 3 2 1 0 R MDPE BF ABRT SSI SIR R IID x 0 0 0 0 0 x 0 R Reserved 7 MDPE Master Data Parity Error 6 BF Bus Fault 5 ABRT Aborted 4 SSI Single Step Interrupt 3 SIR SCRIPTS Interrupt Instruction Received 2 R Reserved 1 IID Illegal Instruction Detected 0 This register contains the interrupt mask bits corresponding to the interrupting conditions described in the DMA Status (DSTAT) register.
For more information on interrupts, see Chapter 2, “Functional Description”. Register: 0x3A Scratch Byte Register (SBR) Read/Write 7 0 SBR 0 0 SBR 0 0 0 0 0 0 Scratch Byte Register [7:0] This is a general purpose register. Apart from CPU access, only register Read/Write and Memory Moves into this register alter its contents. The default value of this register is zero. This register is called the DMA Watchdog Timer on previous LSI53C8XX family products.
the LSI53C875A to make more efficient use of the system PCI bus, thus improving overall system performance. The unit will flush whenever the PFF bit is set, as well as on all transfer control instructions when the transfer conditions are met, on every write to the DMA SCRIPTS Pointer (DSP), on every regular MMOV instruction, and when any interrupt is generated.
STD Start DMA Operation 2 The LSI53C875A fetches a SCSI SCRIPTS instruction from the address contained in the DMA SCRIPTS Pointer (DSP) register when this bit is set.
Registers: 0x3C–0x3F Adder Sum Output (ADDER) Read Only 31 0 ADDER 0 0 0 0 0 0 0 0 0 0 0 0 ADDER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Adder Sum Output [31:0] This register contains the output of the internal adder, and is used primarily for test purposes. The power-up value for this register is indeterminate. It is used to determine if the correct memory address was calculated for a relative jump SCRIPTS instruction.
CMP Function Complete Indicates full arbitration and selection sequence is completed. 6 SEL Selected 5 Indicates the LSI53C875A is selected by a SCSI initiator device. Set the Enable Response to Selection bit in the SCSI Chip ID (SCID) register for this to occur. RSL Reselected 4 Indicates the LSI53C875A is reselected by a SCSI target device. Set the Enable Response to Reselection bit in the SCSI Chip ID (SCID) register for this to occur.
RST SCSI Reset Condition 1 Indicates assertion of the SRST/ signal by the LSI53C875A or any other SCSI device. This condition is edge-triggered, so multiple interrupts cannot occur because of a single SRST/ pulse. PAR SCSI Parity Error 0 Indicates detection by the LSI53C875A of a parity error while receiving or sending SCSI data. See the Disable Halt on Parity Error or SATN/ Condition bits in the SCSI Control One (SCNTL1) register for more information on when this condition is actually raised.
HTH Handshake-to-Handshake Timer Expired 0 The handshake-to-handshake timer is expired. The time measured is the SCSI Request-to-Request (target) or Acknowledge-to-Acknowledge (initiator) period. See the description of the SCSI Timer Zero (STIME0) register, bits [7:4], for more information on the handshaketo-handshake timer.
target. In target mode, this bit is set when the SATN/ signal is asserted by the initiator. CMP Function Complete 6 This bit is set when an arbitration only or full arbitration sequence is completed. SEL Selected 5 This bit is set when the LSI53C875A is selected by another SCSI device.
• Residual data in the synchronous data FIFO – a transfer other than synchronous data receive is started with data left in the synchronous data FIFO. UDC Unexpected Disconnect 2 This bit is set when the LSI53C875A is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the LSI53C875A operates in the initiator mode. When the LSI53C875A operates in low level mode, any disconnect causes an interrupt, even a valid SCSI disconnect.
(SIEN1) register or not. Each bit that is set indicates an occurrence of the corresponding condition. Reading the SIST1 clears the interrupt condition. R Reserved [7:3] STO Selection or Reselection Time-out 2 The SCSI device which the LSI53C875A is attempting to select or reselect does not respond within the programmed time-out period. See the description of the SCSI Timer Zero (STIME0) register, bits [3:0], for more information on the time-out timer.
check byte are received from the SCSI bus (all signals are shown active HIGH): Data Bytes – Running SLPAR 00000000 1. 11001100 11001100 (XOR of word 1) 2. 01010101 10011001 (XOR of word 1 and 2) 3. 00001111 10010110 (XOR of word 1, 2 and 3) Even Parity 4. 10010110 00000000 A one in any bit position of the final SLPAR value would indicate a transmission error. The SLPAR register is also used to generate the check bytes for SCSI send operations.
Which byte is accessed is controlled by the SLPHBEN bit in the SCSI Control Two (SCNTL2) register. Register: 0x45 SCSI Wide Residue (SWIDE) Read/Write 7 0 SWIDE x x SWIDE x x x x x x SCSI Wide Residue [7:0] After a wide SCSI data receive operation, this register contains a residual data byte if the last byte received was never sent across the DMA bus.
DWR Data Write 3 This bit is used to define if a data write is considered to be a local memory access. DRD Data Read 2 This bit is used to define if a data read is considered to be a local memory access. PSCPT Pointer SCRIPTS 1 This bit is used to define if a pointer to a SCRIPTS indirect or table indirect fetch is considered to be a local memory access. SCPTS SCRIPTS This bit is used to define if a SCRIPTS fetch is considered to be a local memory access.
LEDC LED_CNTL 5 The internal connected signal (bit 3 of the Interrupt Status Zero (ISTAT0) register) will be presented on GPIO0 if this bit is set and bit 6 of GPCNTL0 is cleared and the chip is not in progress of performing an EEPROM autodownload regardless of the state of bit 0 (GPIO0). This provides a hardware solution to driving a SCSI activity LED in many implementations of LSI Logic SCSI chips.
HTH [3:0] SEL [3:0] GEN [3:0] Minimum Time-out (80 MHz Clock) With Scale Factor Bit Cleared1 Minimum Time-out (80 MHz Clock) With Scale Factor Bit Set 0000 Disabled Disabled 0001 100 µs 1.6 ms 0010 200 µs 3.2 ms 0011 400 µs 6.4 ms 0100 800 µs 12.8 ms 0101 1.6 ms 25.6 ms 0110 3.2 ms 51.2 ms 0111 6.4 ms 102.4 ms 1000 12.8 ms 204.8 ms 1001 25.6 ms 409.6 ms 1010 51.2 ms 819.2 ms 1011 102.4 ms 1.6 s 1100 204.8 ms 3.2 s 1101 409.6 ms 6.4 s 1110 819.2 ms 12.
Register: 0x49 SCSI Timer One (STIME1) Read/Write 7 6 5 4 R HTHBA GENSF HTHSF x 0 0 0 3 0 GEN[3:0] 0 0 0 0 R Reserved HTHBA Handshake-to-Handshake Timer Bus Activity Enable 6 Setting this bit causes this timer to begin testing for SCSI REQ/, ACK/ activity as soon as SBSY/ is asserted, regardless of the agents participating in the transfer. GENSF General Purpose Timer Scale Factor 5 Setting this bit causes this timer to shift by a factor of 16.
Register: 0x4A Response ID Zero (RESPID0) Read/Write 7 0 RESPID0 x x RESPIO0 x x x x x x Response ID Zero [7:0] RESPID0 and Response ID One (RESPID1) contain the selection or reselection IDs. In other words, these two 8-bit registers contain the ID that the chip responds to on the SCSI bus. Each bit represents one possible ID with the most significant bit of RESPID1 representing ID 15 and the least significant bit of RESPID0 representing ID 0.
chip can arbitrate with only one ID value in the SCID register. Register: 0x4C SCSI Test Zero (STEST0) Read Only 7 4 SSAID x x x x 3 2 1 0 SLT ART SOZ SOM 0 x 1 1 SSAID SCSI Selected As ID [7:4] These bits contain the encoded value of the SCSI ID that the LSI53C875A is selected during a SCSI selection phase. These bits work in conjunction with the Response ID Zero (RESPID0) and Response ID One (RESPID1) registers, which contain the allowable IDs that the LSI53C875A can respond to.
SOM SCSI Synchronous Offset Maximum 0 This bit indicates that the current synchronous SREQ/, SACK/ offset is the maximum specified by bits [3:0] in the SCSI Transfer (SXFER) register. This bit is not latched and may change at any time. It is used in low level synchronous SCSI operations. When this bit is set, the LSI53C875A, as a target, is waiting for the initiator to acknowledge the data transfers. If the LSI53C875A is an initiator, then the target has sent the offset number of requests.
QSEL SCLK Quadrupler Select 2 This bit, when set, selects the output of the internal clock quadrupler for use as the internal SCSI clock. When cleared, this bit selects the clock presented on SCLK for use as the internal SCSI clock.
SZM SCSI High Impedance Mode 3 Setting this bit places all the open drain 48 mA SCSI drivers into a high impedance state. This is to allow internal loopback mode operation without affecting the SCSI bus. AWS Always Wide SCSI 2 When this bit is set, all SCSI information transfers are done in 16-bit wide mode. This includes data, message, command, status and reserved phases. Normally, deassert this bit since 16-bit wide message, command, and status phases are not supported by the SCSI specifications.
Register: 0x4F SCSI Test Three (STEST3) Read/Write 7 6 5 4 3 2 1 0 TE STR HSC DSI S16 TTM CSF STW 0 0 0 0 x 0 0 0 TE TolerANT Enable 7 Setting this bit enables the active negation portion of LSI Logic TolerANT technology. Active negation causes the SCSI Request, Acknowledge, Data, and Parity signals to be actively deasserted, instead of relying on external pull-ups, when the LSI53C875A is driving these signals.
for test purposes or to lower IDD during a power-down mode. 4-92 DSI Disable Single Initiator Response 4 If this bit is set, the LSI53C875A ignores all bus-initiated selection attempts that employ the single initiator option from SCSI-1. In order to select the LSI53C875A while this bit is set, the LSI53C875A’s SCSI ID and the initiator’s SCSI ID must both be asserted. Assert this bit in SCSI-2 systems so that a single bit error on the SCSI bus is not interpreted as a single initiator response.
STW SCSI FIFO Test Write 0 Setting this bit places the SCSI core into a test mode in which the FIFO is easily read or written. While this bit is set, writes to the least significant byte of the SCSI Output Data Latch (SODL) register cause the entire word contained in the SODL to be loaded into the FIFO. These functions are summarized in the table below.
Register: 0x52 SCSI Test Four (STEST4) Read Only 7 6 5 R x 4 0 LOCK x R 0 x x x x x R Reserved [7:6] LOCK Frequency Lock 5 This bit is used when enabling the SCSI clock quadrupler, which allows the LSI53C875A to transfer data at Ultra SCSI rates. Poll this bit for a 1 to determine that the clock quadrupler has locked. For more information on enabling the clock quadrupler, refer to the descriptions of SCSI Test One (STEST1), bits 2 and 3.
Register: 0x56 Chip Control 0 (CCNTL0) Read/Write 7 6 5 4 ENPMJ PMJCTL ENNDJ DISFC 0 0 0 0 ENPMJ 3 2 R x x 1 0 DILS R 0 x Enable Phase Mismatch Jump 7 Upon setting this bit, any phase mismatches do not interrupt but force a jump to an alternate location to handle the phase mismatch.
ENNDJ Enable Jump on Nondata Phase Mismatches 5 This bit controls whether or not a jump is taken during a nondata phase mismatch (i.e. message in, message out, status, or command). When this bit is clear, jumps will only be taken on Data-In or Data-Out phases and a phase mismatch interrupt will be generated for all other phases. When this bit is set, jumps will be taken regardless of the phase in the block move.
Register: 0x57 Chip Control 1 (CCNTL1) Read/Write 7 6 R ZMODE 0 4 x x x 3 2 1 0 DDAC 64TIMOD EN64TIBMV EN64DBMV 0 0 0 0 ZMODE High Impedance Mode 7 Setting this bit causes the LSI53C875A to place all output and bidirectional pins except MAC/_TESTOUT, into a high impedance state. Also, setting this bit causes all I/O pins to become inputs, and all pull-ups and pull-downs to be disabled.
Index Mode 1 (64TIMOD set) table entry format: [31:24] [23:0] Src/Dest Addr [39:32] Byte Count Source/Destination Address [31:0] EN64TIBMV Enable 64-Bit Table Indirect BMOV 1 Setting this bit enables 64-bit addressing for Table Indirect BMOVs using the upper byte (bit [24:31]) of the first Dword of the table entry. When this bit is cleared table indirect BMOVs will use the Static Block Move Selector (SBMS) register to obtain the upper 32 bits of the data address.
Register: 0x5A–0x5B Reserved Registers: 0x5C–0x5F Scratch Register B (SCRATCHB) Read/Write 31 0 SCRATCHB x x x x x x x x x x x SCRATCHB x x x x x x x x x x x x x x x x x x x x x Scratch Register B [31:0] This is a general purpose user definable scratch pad register. Apart from CPU access, only register Read/Write and Memory Moves directed at the SCRATCH register will alter its contents. The power-up values are indeterminate.
operation is performed, one of the six selector registers below will be used to generate a 64-bit address. If the selector for a particular device operation is zero, then a standard 32-bit address cycle will be generated. If the selector value is nonzero, then a DAC will be issued and the 64-bit address will be presented in two address phases.
Registers: 0xA4–0xA7 Memory Move Write Selector (MMWS) Read/Write 31 0 MMWS 0 0 0 0 0 0 0 0 0 0 0 0 MMWS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Memory Move Write Selector [31:0] Supplies the upper Dword of a 64-bit address during data write operations during Memory-to-Memory Moves and absolute address STORE operations. A special mode of this register can be enabled by setting the PCI Configuration Into Enable bit in the Chip Test Two (CTEST2) register.
Writes to the SFS register are unaffected. Clearing the PCI Configuration Into Enable bit causes the SFS register to return to normal operation. Registers: 0xAC–0xAF DSA Relative Selector (DRS) Read/Write 31 0 DRS 0 0 0 0 0 0 0 0 0 0 0 0 DRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSA Relative Selector [31:0] Supplies the upper Dword of a 64-bit address during table indirect fetches and Load and Store Data Structure Address (DSA) relative operations.
Registers: 0xB4–0xB7 Dynamic Block Move Selector (DBMS) Read/Write 31 0 DBMS 0 0 0 0 0 0 0 0 0 0 0 0 DBMS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Dynamic Block Move Selector [31:0] Supplies the upper Dword of a 64-bit address during block move operations, reads or writes. This register is used only during 64-bit direct BMOV instructions and will be reloaded with the upper 32-bit data address upon execution of a 64-bit direct BMOVs.
Registers: 0xC0–0xC3 Phase Mismatch Jump Address 1 (PMJAD1) Read/Write 31 0 PMJAD1 0 0 0 0 0 0 0 0 0 0 0 0 PMJAD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Phase Mismatch Jump Address 1 [31:0] This register contains the 32-bit address that will be jumped to upon a phase mismatch.
Registers: 0xC8–0xCB Remaining Byte Count (RBC) Read/Write 31 0 RBC 0 0 0 0 0 0 0 0 0 0 0 0 RBC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remaining Byte Count (RBC) [31:0] This register contains the byte count that remains for the BMOV that was executing when the phase mismatch occurred. In the case of direct or indirect BMOV instructions, the upper byte of this register will also contain the opcode of the BMOV that was executing.
In the case of a SCSI data receive, if there is a byte in the SCSI Wide Residue (SWIDE) register then this address will point to the location where that byte must be stored. The SWIDE byte must be manually written to memory and this address must be incremented prior to updating any scatter/gather entry. In the case of a SCSI data receive, if there is not a byte in the SWIDE register then this address will be the next location that should be written to when this I/O restarts.
Registers: 0xD4–0xD7 Instruction Address (IA) Read/Write 31 0 IA 0 0 0 0 0 0 0 0 0 0 0 0 IA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Instruction Address [31:0] This register always contains the address of the BMOV instruction that was executing when the phase mismatch occurred.
cannot be counted for this BMOV as it was actually part of the byte count for the previous BMOV. Register: 0xDB Reserved Registers: 0xDC–0xDF Cumulative SCSI Byte Count (CSBC) Read/Write 31 0 CSBC 0 0 0 0 0 0 0 0 0 0 0 CSBC 0 0 0 0 0 0 4-108 Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Cumulative SCSI Byte Count [31:0] This loadable register contains a cumulative count of the actual number of bytes that have been transferred across the SCSI bus during data phases, i.e.
Chapter 5 SCSI SCRIPTS Instruction Set The LSI53C875A contains a SCSI SCRIPTS processor that permits both DMA and SCSI commands to be fetched from host memory or internal SCRIPTS RAM. Algorithms written in SCSI SCRIPTS control the actions of the SCSI and DMA cores. The SCRIPTS processor executes complex SCSI bus sequences independently of the host CPU. This chapter describes the SCSI SCRIPTS Instruction Set used to write these algorithms.
require certain unique timings or bus sequences to operate properly. Another feature allowed at the low level is loopback testing. In loopback mode, the SCSI core can be directed to talk to the DMA core to test internal data paths all the way out to the chip’s pins. 5.2 High Level SCSI SCRIPTS Mode To operate in the SCSI SCRIPTS mode, the LSI53C875A requires only a SCRIPTS start address. The start address must be at a Dword (four byte) boundary.
Table 5.1 SCRIPTS Instructions Instruction Description Block Move Block Move instruction moves data between the SCSI bus and memory. I/O or Read/Write I/O or Read/Write instructions cause the LSI53C875A to trigger common SCSI hardware sequences, or to move registers. Transfer Control Transfer Control instruction allows SCRIPTS instructions to make decisions based on real time SCSI bus conditions.
• The LSI53C875A typically fetches two Dwords (64 bits) and decodes the high order byte of the first longword as a SCRIPTS instruction. If the instruction is a Block Move, the lower three bytes of the first longword are stored and interpreted as the number of bytes to be moved. The second longword is stored and interpreted as the 32-bit beginning address in main memory to which the move is directed.
Figure 5.
5.3 Block Move Instruction Performing a Block Move instruction, bit 5, Source I/O - Memory Enable (SIOM) and bit 4, Destination I/O - Memory Enable (DIOM) in the DMA Mode (DMODE) register determines whether the source/destination address resides in memory or I/O space. When data is being moved onto the SCSI bus, SIOM controls whether that data comes from I/O or memory space. When data is being moved off of the SCSI bus, DIOM controls whether that data goes to I/O or memory space. 5.3.
Direct Addressing The byte count and absolute address are: Command Byte Count Address of Data Indirect Addressing Use the fetched byte count, but fetch the data address from the address in the instruction. Command Byte Count Address of Pointer to Data Once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. This indirect feature allows a table of data buffer addresses to be specified.
the data structure. Sign extended values of all ones for negative values are allowed, but bits [31:24] are ignored. Note: Command Not Used Don’t Care Table Offset Do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. Prior to the start of an I/O, the Data Structure Address (DSA) register should be loaded with the base address of the I/O data structure. The address may be any address on a longword boundary.
OPC OpCode 27 This 1-bit OpCode field defines the type of Block Move (MOVE) Instruction to be preformed in Target and Initiator mode. Target Mode In Target mode, the OpCode bit defines the following operations: OPC Instruction Defined 0 MOVE/MOVE64 1 CHMOV/CHMOV64 These instructions perform the following steps: 1. The LSI53C875A verifies that it is connected to the SCSI bus as a Target before executing this instruction. 2.
register contains 0x000000, an illegal instruction interrupt is generated. 4. The LSI53C875A transfers the number of bytes specified in the DBC register starting at the address specified in the DMA Next Address (DNAD) register. If the OpCode bit is set and a data transfer ends on an odd byte boundary, the LSI53C875A stores the last byte in the SCSI Wide Residue (SWIDE) register during a receive operation.
register. These phase lines are latched when SREQ/ is asserted. 4. If the SCSI phase bits match the value stored in the SCSI SCSI Status One (SSTAT1) register, the LSI53C875A transfers the number of bytes specified in the DMA Byte Counter (DBC) register starting at the address pointed to by the DMA Next Address (DNAD) register.
TC[23:0] Table 5.2 SCSI Information Transfer Phase MSG C_D I_O SCSI Phase 0 0 0 Data-Out 0 0 1 Data-In 0 1 0 Command 0 1 1 Status 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Message-Out 1 1 1 Message-In Transfer Counter [23:0] This 24-bit field specifies the number of data bytes to be moved between the LSI53C875A and system memory. The field is stored in the DMA Byte Counter (DBC) register.
5.3.2 Second Dword 31 0 DMA SCRIPTS Pointer Save (DSPS) Register x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Start Address [31:0] This 32-bit field specifies the starting address of the data to move to/from memory. This field is copied to the DMA Next Address (DNAD) register. When the LSI53C875A transfers data to or from memory, the DNAD register is incremented by the number of bytes transferred.
5.4.1 First Dword 31 30 29 27 26 25 24 23 20 19 16 15 DMA Command (DCMD) Register 1 x x x x x x 8 7 6 5 4 3 R ACK R ATN 0 0 x 0 0 x 2 0 DMA Byte Counter (DBC) Register IT[1:0] OPC[2:0] RA TI Sel 0 11 10 9 R 0 0 ENDID[3:0] 0 0 x x x x R CC TM 0 0 0 0 0 x x R 0 0 0 IT[1:0] Instruction Type - I/O Instruction [31:30] The IT bit configuration (01) defines an I/O Instruction Type.
This way the SCRIPTS can move on to the next instruction before the reselection completes. It continues executing SCRIPTS until a SCRIPT that requires a response from the Initiator is encountered. If the LSI53C875A is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the DMA Next Address (DNAD) register.
When the SACK/ or SATN/ bits are cleared, the corresponding bits are cleared in the SCSI Output Control Latch (SOCL) register. Do not set SACK/ or SATN/ except for testing purposes. When the target bit is cleared, the corresponding bit in the SCSI Control Zero (SCNTL0) register is cleared. When the carry bit is cleared, the corresponding bit in the ALU is cleared. Note: None of the signals are cleared on the SCSI bus in the Target mode.
the LSI53C875A to Initiator mode if it is reselected, or to Target mode if it is selected. If the Select with SATN/ field is set, the SATN/ signal is asserted during the selection phase. Wait Disconnect Instruction The LSI53C875A waits for the Target to perform a “legal” disconnect from the SCSI bus. A “legal” disconnect occurs when SBSY/ and SSEL/ are inactive for a minimum of one Bus Free delay (400 ns), after the LSI53C875A receives a Disconnect Message or a Command Complete Message.
RA Relative Addressing Mode 26 When this bit is set, the 24-bit signed value in the DMA Next Address (DNAD) register is used as a relative displacement from the current DMA SCRIPTS Pointer (DSP) address. Use this bit only in conjunction with the Select, Reselect, Wait Select, and Wait Reselect instructions. The Select and Reselect instructions can contain an absolute alternate jump address or a relative transfer address.
Use this bit only in conjunction with the Select, Reselect, Wait Select, and Wait Reselect instructions. Use bits 25 and 26 individually or in= combination to produce the following conditions: Bit 25 Bit 26 Direct 0 0 Table Indirect 0 1 Relative 1 0 Table Relative 1 1 Direct Uses the device ID and physical address in the instruction. Command ID Not Used Not Used Absolute Alternate Address Table Indirect Uses the physical jump address, but fetches data using the table indirect method.
Table Relative Treats the alternate jump address as a relative jump and fetches the device ID, synchronous offset, and synchronous period indirectly. The value in bits [23:0] of the first four bytes of the SCRIPTS instruction is added to the data structure base address to form the fetch address. Command Table Offset Absolute Jump Offset 5-20 Sel Select with ATN/ 24 This bit specifies whether SATN/ is asserted during the selection phase when the LSI53C875A is executing a Select instruction.
R Reserved [8:7] ACK Set/Clear SACK/ R Reserved ATN Set/Clear SATN/ 3 These two bits are used in conjunction with a Set or Clear instruction to assert or deassert the corresponding SCSI control signal. Bit 6 controls the SCSI SACK/ signal. Bit 3 controls the SCSI SATN/ signal. 6 [5:4] The Set instruction is used to assert SACK/ and/or SATN/ on the SCSI bus. The Clear instruction is used to deassert SACK/ and/or SATN/ on the SCSI bus.
If relative or table relative addressing is used, this value is a 24-bit signed offset relative to the current DMA SCRIPTS Pointer (DSP) register value. 5.5 Read/Write Instructions The Read/Write instruction supports addition, subtraction, and comparison of two separate values within the chip. It performs the desired operation on the specified register and the SCSI First Byte Received (SFBR) register, then stores the result back to the specified register or the SFBR.
A[6:0] Register Address - A[6:0] [22:16] It is possible to change register values from SCRIPTS in read-modify-write cycles or move to/from SFBR cycles. A[6:0] selects an 8-bit source/destination register within the LSI53C875A. ImmD Immediate Data [15:8] This 8-bit value is used as a second operand in logical and arithmetic functions. A7 Upper Register Address Line [A7] This bit is used to access registers 0x80–0xFF. R Reserved 7 [6:0] 5.5.
5.5.4 Move To/From SFBR Cycles All operations are read-modify-writes. However, two registers are involved, one of which is always the SFBR. Table 5.3 shows the possible read-modify-write operations. The possible functions of this instruction are: Table 5.3 • Write one byte (value contained within the SCRIPTS instruction) into any chip register. • Move to/from the SFBR from/to any other register. • Alter the value of a register with AND, OR, ADD, XOR, SHIFT LEFT, or SHIFT RIGHT operators.
Table 5.3 Read/Write Instructions (Cont.) OpCode 111 Read-Modify-Write OpCode 110 Move to SFBR OpCode 101 Move from SFBR 100 AND data with register and place the result in the same register. Syntax: “Move RegA & data8 to RegA” AND data with register and place the result in the SCSI First Byte Received (SFBR) register. Syntax: “Move RegA & data8 to SFBR” AND data with SFBR and place the result in the register.
5.6.1 First Dword 31 30 29 27 26 24 23 22 21 20 19 18 17 DMA Command (DCMD) Register 16 15 0 x x x x x x 0 DMA Byte Counter (DBC) Register DCM-Data Compare Mask IT[1:0] OPC[2:0] SCSIP[2:0] RA R CT IF JMP CD CP WVP 1 8 7 x 0 x x x x x x x x x x x x x x DCV-Data Compare Value x x x x x x x x IT[1:0] Instruction Type - Transfer Control Instruction [31:30] The IT bit configuration (10) defines the Transfer Control Instruction Type.
DMA SCRIPTS Pointer Save (DSPS) register. The DSP register now contains the address of the next instruction. If the comparisons are false, the LSI53C875A fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer (DSP) register, leaving the instruction pointer unchanged. Call Instruction The LSI53C875A can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare, and True/False bit fields.
If the comparisons are false, the LSI53C875A fetches the next instruction from the address pointed to by the DSP register and the instruction pointer is not modified. Interrupt Instruction The LSI53C875A can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare, and True/False bit fields. If the comparisons are true, the LSI53C875A generates an interrupt by asserting the IRQ/ signal.
Table 5.5 RA SCSI Phase Comparisons MSG C/D I/O SCSI Phase 0 0 0 Data-Out 0 0 1 Data-In 0 1 0 Command 0 1 1 Status 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Message-Out 1 1 1 Message-In Relative Addressing Mode 23 When this bit is set, the 24-bit signed value in the DMA SCRIPTS Pointer Save (DSPS) register is used as a relative offset from the current DMA SCRIPTS Pointer (DSP) address (which is pointing to the next instruction, not the one currently executing).
signed (2’s complement), the jump can be forward or backward. A relative transfer can be to any address within a 16 Mbyte segment. The program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new execution address. SCRIPTS programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing SCRIPTS.
CD Bit 19 Result of Compare 0 False Jump Taken 0 True No Jump 1 False No Jump 1 True Jump Taken Action Compare Data 18 When this bit is set, the first byte received from the SCSI data bus (contained in the SCSI First Byte Received (SFBR) register) is compared with the Data to be Compared Field in the Transfer Control instruction. The Wait for Valid Phase bit controls when this compare occurs. The Jump if True/False bit determines the condition (true or false) to branch on.
DCV Data Compare Value [7:0] This 8-bit field is the data compared against the register. These bits are used in conjunction with the Data Compare Mask Field to test for a particular data value. 5.6.2 Second Dword 31 0 DMA SCRIPTS Pointer Save (DSPS) Register x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Jump Address [31:0] This 32-bit field contains the address of the next instruction to fetch when a jump is taken.
• Indirect addresses are not allowed. A burst of data is fetched from the source address, put into the DMA FIFO and then written out to the destination address. The move continues until the byte count decrements to zero, then another SCRIPTS is fetched from system memory. The DMA SCRIPTS Pointer Save (DSPS) and Data Structure Address (DSA) registers are additional holding registers used during the Memory Move. However, the contents of the Data Structure Address (DSA) register are preserved. 5.7.
5.7.2 Read/Write System Memory from SCRIPTS By using the Memory Move instruction, single or multiple register values are transferred to or from system memory. Because the LSI53C875A responds to addresses as defined in the Base Address Register Zero (I/O) or Base Address Register One (MEMORY) registers, it can be accessed during a Memory Move operation if the source or destination address decodes to within the chip’s register space.
5.7.4 Third Dword 31 0 Temporary (TEMP) Register x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x TEMP Register [31:0] These bits contain the destination address for the Memory Move. 5.8 Load and Store Instructions The Load and Store instructions provide a more efficient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction.
The SIOM and DIOM bits in the DMA Mode (DMODE) register determine whether the destination or source address of the instruction is in Memory space or I/O space, as illustrated in the following table. The Load and Store utilizes the PCI commands for I/O read and I/O write to access the I/O space. Bit Source Destination SIOM (Load) Memory Register DIOM (Store) Register Memory 5.8.
Note: This bit has no effect unless the Prefetch Enable bit in the DMA Control (DCNTL) register is set. LS Load and Store 24 When this bit is set, the instruction is a Load. When cleared, it is a Store. R Reserved RA[6:0] Register Address [22:16] A[6:0] selects the register to Load and Store to/from within the LSI53C875A. R Reserved BC Byte Count [2:0] This value is the number of bytes to Load and Store. 23 [15:3] 5.8.
5-38 SCSI SCRIPTS Instruction Set
Chapter 6 Electrical Specifications This section specifies the LSI53C875A electrical and mechanical characteristics. It is divided into the following sections: • Section 6.1, “DC Characteristics” • Section 6.2, “TolerANT Technology Electrical Characteristics” • Section 6.3, “AC Characteristics” • Section 6.4, “PCI and External Memory Interface Timing Diagrams” • Section 6.5, “SCSI Timing Diagrams” • Section 6.6, “Package Diagrams” 6.
Table 6.1 Symbol Absolute Maximum Stress Ratings1 Parameter Min Max Unit Test Conditions TSTG Storage temperature −55 150 °C – VDD Supply voltage −0.5 4.5 V – VIN Input voltage VSS −0.3 5.55 V SCSI 5 V TolerANT pads ILP2 Latch-up current ±=150 – mA – ESD Electrostatic discharge – 2K V MIL-STD 883C, Method 3015.7 1. Stresses beyond those listed above may cause permanent damage to the device.
Table 6.4 Symbol Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/ Parameter Min Max Unit Test Conditions VIH Input high voltage 2.0 5.25 V – VIL Input low voltage VSS −0.5 0.8 V – VOH Output high voltage 2.4 VDD V −4 mA VOL Output low voltage VSS 0.4 V 4 mA IOZ 3-state leakage −10 10 µA – Pull-down current 12.5 +50 µA – IPULL Table 6.
Table 6.6 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Symbol Parameter Min Max Unit Test Conditions VIH Input high voltage 0.5 VDD 5.25 V – VIL Input low voltage VSS 0.3 VDD V – VOH Output high voltage 0.9 VDD VDD V −16 mA VOL Output low voltage VSS 0.1 VDD V 16 mA IOZ 3-state leakage −10 10 µA – Pull-down current 25 – µA – IPULL Table 6.
Table 6.9 Symbol Output Signals—IRQ/, MAC/_TESTOUT, REQ/ Parameter Min Max Unit Test Conditions VOH Output high voltage 0.9 VDD VDD V −16 mA VOL Output low voltage VSS 0.1 VDD V 16 mA IOZ 3-state leakage −10 10 µA – Pull-down current - only on IRQ/ −50 −12.5 µA – Parameter Min Max Unit Test Conditions VOL Output low voltage VSS 0.1 VDD V 16 mA IOZ 3-state leakage −10 10 µA – IPULL Table 6.10 Symbol Output Signal—SERR/ 6.
Table 6.11 Symbol TolerANT Technology Electrical Characteristics for SE SCSI Signals Parameter Min1 Max Unit Test Conditions VOH2 Output high voltage 2.0 VDD +0.3 V IOH = 7 mA VOL Output low voltage VSS 0.5 V IOL = 48 mA VIH Input high voltage 2.0 VDD +0.3 V – VIL Input low voltage VSS −0.3 0.8 V Referenced to VSS VIK Input clamp voltage −0.66 −0.77 V VDD = 4.75; II = −20 mA VTH Threshold, HIGH to LOW 1.0 1.2 V – VTL Threshold, LOW to HIGH 1.4 1.
Figure 6.1 Rise and Fall Time Test Condition 47 Ω 20 pF + − Figure 6.2 2.5 V SCSI Input Filtering t1 REQ/ or SACK/ Input VTH Note: t1 is the input filtering period. Figure 6.3 Hysteresis of SCSI Receivers Received Logic Level 1.1 1.3 1 0 1.5 1.
Figure 6.4 Input Current as a Function of Input Voltage +40 Input Current (milliAmperes) +20 14.4 V 8.2 V 0 −0.7 V HIGH-Z OUTPUT −20 ACTIVE −40 −4 0 4 8 12 16 Input Voltage (Volts) Figure 6.
6.3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to the DC Characteristics section). Chip timings are based on simulation at worst case voltage, temperature, and processing. Timing was developed with a load capacitance of 50 pF. Table 6.12 and Figure 6.6 provide external clock timing data. Table 6.
Table 6.13 and Figure 6.7 provide Reset Input timing data. Table 6.13 Symbol Reset Input Parameter Min Max Unit t1 Reset pulse width 10 – tCLK t2 Reset deasserted setup to CLK HIGH 0 – ns t3 MAD setup time to CLK HIGH (for configuring the MAD bus only) 20 – ns t4 MAD hold time from CLK HIGH (for configuring the MAD bus only) 20 – ns Figure 6.7 Reset Input CLK t1 t2 RST/ t3 MAD1 t4 Valid Data Note: 1. When enabled. Table 6.14 and Figure 6.
Figure 6.8 Interrupt Output t2 t3 t1 IRQ/ CLK 6.4 PCI and External Memory Interface Timing Diagrams Figure 6.9 through Figure 6.32 represent signal activity when the LSI53C875A accesses the PCI bus. This section includes timing diagrams for access to three groups of memory configurations. The first group applies to Target Timing. The second group applies to Initiator Timing. The third group applies to External Memory Timing.
• 6-12 – Burst Read, 32-Bit Address and Data – Burst Read, 64-Bit Address and Data – Burst Write, 32-Bit Address and Data – Burst Write, 64-Bit Address and 32-Bit Data External Memory Timing – External Memory Read – External Memory Write – Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle – Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle – Nornal/Fast Memory (≥ 128 Kbytes) Multiple Byte Access Read Cycle – Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte Ac
6.4.1 Target Timing The tables and figures in this section describe target timings. Table 6.15 Symbol PCI Configuration Register Read Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid – 11 ns Figure 6.
Table 6.16 Symbol PCI Configuration Register Write Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid – 11 ns Figure 6.
Table 6.17 Symbol 32-Bit Operating Register/SCRIPTS RAM Read Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid – 11 ns Figure 6.
Table 6.18 Symbol 64-Bit Address Operating Register/SCRIPTS RAM Read Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid – 11 ns Figure 6.
Table 6.19 Symbol 32-Bit Operating Register/SCRIPTS RAM Write Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid – 11 ns Figure 6.
Table 6.20 Symbol 64-Bit Address Operating Register/SCRIPTS RAM Write Parameter Min Max Unit t1 Shared signal input setup time 7 – ns t2 Shared signal input hold time 0 – ns t3 CLK to shared signal output valid – 11 ns Figure 6.
6.4.2 Initiator Timing The tables and figures in this section describe LSI53C875A initiator timings. Table 6.
Figure 6.
Table 6.
Figure 6.
Table 6.
Figure 6.
Table 6.
Figure 6.
Table 6.
Figure 6.
Table 6.
Figure 6.
Table 6.
Figure 6.
Table 6.
Figure 6.
6.4.3 External Memory Timing The tables and figures in this section describe LSI53C875A external timings. The External Memory Write timings start on page 6-40. Table 6.
Figure 6.
Figure 6.23 External Memory Read (Cont.
Table 6.
The External Memory Write timings start on page 6-40.
Figure 6.
Figure 6.24 External Memory Write (Cont.
Table 6.
Table 6.
Figure 6.
Figure 6.27 Normal/Fast Memory (≥= 128 Kbytes) Multiple Byte Access Read Cycle (Cont.
Figure 6.
Figure 6.28 Normal/Fast Memory (≥= 128 Kbytes) Multiple Byte Access Write Cycle (Cont.
Table 6.33 Symbol Slow Memory (≤= 128 Kbytes) Read Cycle Parameter Min Max Unit t11 Address setup to MAS/ HIGH 25 – ns t12 Address hold from MAS/ HIGH 15 – ns t13 MAS/ pulse width 25 – ns t14 MCE/ LOW to data clocked in 150 – ns t15 Address valid to data clocked in 205 – ns t16 MOE/ LOW to data clocked in 100 – ns t17 Data hold from address, MOE/, MCE/ change 0 – ns t18 Address out from MOE/, MCE/ HIGH 50 – ns t19 Data setup to CLK HIGH 5 – ns Figure 6.
Table 6.34 Symbol Slow Memory (≤ 128 Kbytes) Write Cycle Parameter Min Max Unit t11 Address setup to MAS/ HIGH 25 – ns t12 Address hold from MAS/ HIGH 15 – ns t13 MAS/ pulse width 25 – ns t20 Data setup to MWE/ LOW 30 – ns t21 Data hold from MWE/ HIGH 20 – ns t22 MWE/ pulse width 100 – ns t23 Address setup to MWE/ LOW 60 – ns t24 MCE/ LOW to MWE/ HIGH 120 – ns t25 MCE/ LOW to MWE/ LOW 25 – ns t26 MWE/ HIGH to MCE/ HIGH 25 – ns Figure 6.
Table 6.35 Symbol ≤= 64 Kbytes ROM Read Cycle Parameter Min Max Unit t11 Address setup to MAS/ HIGH 25 – ns t12 Address hold from MAS/ HIGH 15 – ns t13 MAS/ pulse width 25 – ns t14 MCE/ LOW to data clocked in 150 – ns t15 Address valid to data clocked in 205 – ns t16 MOE/ LOW to data clocked in 100 – ns t17 Data hold from address, MOE/, MCE/ change 0 – ns t18 Address out from MOE/, MCE/ HIGH 50 – ns t19 Data setup to CLK HIGH 5 – ns Figure 6.
Table 6.36 Symbol ≤= 64 Kbyte ROM Write Cycle Parameter Min Max Unit t11 Address setup to MAS/ HIGH 25 – ns t12 Address hold from MAS/ HIGH 15 – ns t13 MAS/ pulse width 25 – ns t20 Data setup to MWE/ LOW 30 – ns t21 Data hold from MWE/ HIGH 20 – ns t22 MWE/ pulse width 100 – ns t23 Address setup to MWE/ LOW 60 – ns t24 MCE/ LOW to MWE/ HIGH 120 – ns t25 MCE/ LOW to MWE/ LOW 25 – ns t26 MWE/ HIGH to MCE/ HIGH 25 – ns Figure 6.
6.5 SCSI Timing Diagrams The tables and diagrams in this section describe the LSI53C875A SCSI timings. Table 6.37 Symbol Initiator Asynchronous Send Parameter Min Max Unit t1 SACK/ asserted from SREQ/ asserted 5 – ns t2 SACK/ deasserted from SREQ/ deasserted 5 – ns t3 Data setup to SACK/ asserted 55 – ns t4 Data hold from SREQ/ deasserted 0 – ns Figure 6.
Table 6.38 Symbol Initiator Asynchronous Receive Parameter Min Max Unit t1 SACK/ asserted from SREQ/ asserted 5 – ns t2 SACK/ deasserted from SREQ/ deasserted 5 – ns t3 Data setup to SREQ/ asserted 0 – ns t4 Data hold from SACK/ asserted 0 – ns Figure 6.
Table 6.39 Symbol Target Asynchronous Send Parameter Min Max Unit t1 SREQ/ deasserted from SACK/ asserted 5 – ns t2 SREQ/ asserted from SACK/ deasserted 5 – ns t3 Data setup to SREQ/ asserted 55 – ns t4 Data hold from SACK/ asserted 0 – ns Figure 6.
Table 6.40 Symbol Target Asynchronous Receive Parameter Min Max Unit t1 SREQ/ deasserted from SACK/ asserted 5 – ns t2 SREQ/ asserted from SACK/ deasserted 5 – ns t3 Data setup to SACK/ asserted 0 – ns t4 Data hold from SREQ/ deasserted 0 – ns Figure 6.36 Target Asynchronous Receive SREQ/ n+1 n t2 t1 SACK/ n t3 SD[15:0]/, SDP[1:0]/ Table 6.41 Symbol n+1 t4 Valid n Valid n + 1 SCSI-1 Transfers (5.
Table 6.42 Symbol SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.
Figure 6.
6.6 Package Diagrams This section of the manual has a package drawing and pinout for both the PQFP and BGA. Figure 6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing Important: 6-58 This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code P3.
Figure 6.38 160-pin PQFP (P3) Mechanical Drawing (Sheet 2 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code P3.
Table 6.
Figure 6.39 169-Pin BGA Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code GV.
Table 6.
Appendix A Register Summary Table A.
Table A.1 LSI53C875A PCI Register Map (Cont.) Register Name Address Read/Write Page Power Management Capabilities (PMC) 0x42–0x43 Read Only 4-15 Power Management Control/Status (PMCSR) 0x44–0x45 Read/Write 4-16 Reserved 0x28–0x2B – 4-10 Reserved 0x35–0x3B – 4-13 Revision ID (Rev ID) 0x08 Read Only 4-6 Status 0x06–0x07 Read/Write 4-5 Subsystem ID 0x2E–0x2F Read Only 4-11 Subsystem Vendor ID 0x2C–0x2D Read Only 4-10 Vendor ID 0x00–0x01 Read Only 4-2 Table A.
Table A.2 LSI53C875A SCSI Register Map (Cont.
Table A.2 LSI53C875A SCSI Register Map (Cont.
Table A.2 LSI53C875A SCSI Register Map (Cont.
A-6 Register Summary
Appendix B External Memory Interface Diagram Examples Appendix B has example external memory interface diagrams. Figure B.1 16 Kbyte Interface with 200 ns Memory MOE/ OE MCE/ CE MAD[7:0] Bus A[7:0] VDD MAD0 D[7:0] A[13:8] 4.7 K 27C128 8 LSI53C875A MAS0/ 6 MAS1/ D0 Q0 HCT374 D7 Q7 CK QE 8 D0 Q0 HCT374 D5 Q5 CK QE Note: MAD[3:1] pulled LOW internally. MAD bus sense logic enabled for 16 Kbyte of slow memory (200 ns devices @ 33 MHz).
Figure B.2 64 Kbyte Interface with 150 ns Memory Optional - for Flash Memory only, not required for EEPROMS. VPP + 12 V VPP Control GPIO4 MWE/ WE MOE/ OE MCE/ CE MAD[7:0] Bus A[7:0] VDD MAD2 D[7:0] A[15:8] 4.7 K 27C512-15/ 28F512-15/ Socket LSI53C875A 8 MAS0/ 6 MAS1/ D0 Q0 HCT374 D7 Q7 QE CK 8 D0 Q0 HCT374 D7 Q7 CK QE Note: MAD 3, 1, 0 pulled LOW internally. MAD bus sense logic enabled for 64 Kbyte of fast memory (150 ns devices @ 33 MHz).
Figure B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 ns Memory Optional - for Flash Memory only, not required for EEPROMS. VPP + 12 V VPP Control GPIO4 MWE/ WE MOE/ OE MCE/ CE MAD[7:0] Bus A[7:0] VDD MAD3 D[7:0] A[15:8] 4.7 K 27C020-15/ 28F020-15/ Socket A[19:16] LSI53C875A 8 MAS0/ 6 MAS1/ D0 Q0 HCT374 D7 Q7 CK QE 8 D0 Q0 HCT374 D7 Q7 CK QE MAD[3:0] D0 Q0 Bus HCT377 4 Q3 D3 CK E Note: MAD[2:0] pulled LOW internally.
Figure B.4 512 Kbyte Interface with 150 ns Memory Optional - for Flash Memory only, not required for EEPROMS. 27C010-15/28F010-15 Sockets VPP + 12 V VPP Control GPIO4 MWE/ WE WE WE WE OE OE OE OE D[7:0] D[7:0] D[7:0] D[7:0] A0 A0 A0 A0 A16 A16 A16 A16 MOE/ MAD[7:0] Bus VDD MAD3 4.7 K MAD1 4.7 K MAD3 4.7 K LSI53C875A 8 MAS0/ MAS1/ MCE/ A[7:0] D[7:0] A[15:8] . . . . . . . . . . . .
Index Symbols (64TIMOD) 4-97 (A7) 5-23 (AAP) 4-22 (ABRT) 4-40, 4-48 (ACK) 4-37, 4-39 (ADB) 4-23 (ADCK) 4-60 (ADDER) 4-73 (AESP) 4-24 (AIP) 4-43 (APS) 4-16 (ARB[1:0]) 4-20 (ART) 4-87 (ATN) 4-37, 4-39 (AWS) 4-90 (BAR0) 4-9 (BAR1) 4-9 (BAR2) 4-10 (BBCK) 4-61 (BDIS) 4-59 (BF) 4-40, 4-69 (BL[1:0]) 4-66 (BL2) 4-61 (BO) 4-57 (BO[9:8]) 4-62 (BOF) 4-68 (BSE) 4-17 (BSY) 4-37, 4-39 (C_D) 4-37, 4-39, 4-45 (CC) 4-7 (CCF[2:0]) 4-29 (CCNTL0) 4-95 (CCNTL1) 4-97 (CHM) 4-26 (CID) 4-15 (CIO) 4-54 (CLF) 4-56 (CLS) 4-7 (CLSE)
(ERBA) 4-12 (ERL) 4-67 (ERMP) 4-68 (ESA) 4-106 (EWS) 4-29 (EXC) 4-23 (EXT) 4-90 (FBL3) 4-59 (FE) 4-82 (FF[3:0]) 4-43 (FF4) 4-46 (FFL) 4-53 (FLF) 4-56 (FLSH) 4-51 (FM) 4-56 (FMT) 4-53 (GEN) 4-75, 4-79 (GEN[3:0]) 4-85 (GENSF) 4-85 (GPCNTL0) 4-82 (GPIO) 4-35 (GPIO[1:0]) 4-83 (GPIO[4:2]) 4-83 (GPREG0) 4-35 (HSC) 4-91 (HT) 4-8 (HTH) 4-76, 4-79 (HTH[3:0]) 4-83 (HTHBA) 4-85 (HTHSF) 4-85 (I/O) 4-9, 4-37, 4-45 (I_O) 4-39 (IA) 4-107 (IARB) 4-24 (IID) 4-40, 4-69 (IL) 4-13 (ILF) 4-42 (ILF1) 4-46 (INTF) 4-49 (IP) 4-14 (
(SGE) 4-74, 4-77 (SI) 4-51 (SID) 4-11 (SIEN0) 4-73 (SIEN1) 4-75 (SIGP) 4-49, 4-54 (SIOM) 4-67 (SIP) 4-50 (SIR) 4-40 (SIST0) 4-76 (SIST1) 4-78 (SLB) 4-89 (SLPAR) 4-79 (SLPHBEN) 4-27 (SLPMD) 4-27 (SLT) 4-87 (SOCL) 4-37 (SODL) 4-94 (SOM) 4-88 (SOZ) 4-87 (SPL1) 4-47 (SRE) 4-30 (SRST) 4-48 (SRTM) 4-59 (SRUN) 4-51 (SSAID) 4-87 (SSE) 4-5 (SSI) 4-40, 4-69 (SSID) 4-38 (SSM) 4-71 (SST) 4-25 (SSTAT0) 4-42 (SSTAT1) 4-43 (SSTAT2) 4-46 (START) 4-21 (STD) 4-72 (STEST0) 4-87 (STEST1) 4-88 (STEST2) 4-89 (STEST3) 4-91 (STEST
burst (Cont.
DMA interrupt (Cont.
IDSEL 2-3, 3-6 signal 2-5 illegal instruction detected (IID) 4-40, 4-69 immediate arbitration (IARB) 4-24 data 5-23 indirect addressing 5-6 initialization device select 3-6 initiator mode 5-16 phase mismatch 4-76 ready 3-6 input 3-3 capacitance 6-2 instruction address (IA) 4-107 block move 5-6 prefetch unit flushing 2-21 type 5-36 block move 5-6 I/O instruction 5-14 memory move 5-33 read/write instruction 5-22 transfer control instruction 5-26 internal SCRIPTS RAM 2-18 internal RAM see also SCRIPTS RAM 2-18
memory (Cont.
reset 3-4 input 6-10 SCSI offset (ROF) 4-89 response ID one (RESPID1) 4-86 response ID zero (RESPID0) 4-86 return instruction 5-27 revision ID (RID) 4-6 ROM flash and memory interface signals 3-11 pin 2-49 RST/ 3-4 S SACK 2-42 SACK/ status (ACK) 4-39 SACs 2-19 SATN/ status (ATN) 4-39 SBSY/ status (BSY) 4-39 SC_D/ status (C_D) 4-39 SCLK 3-8 (SCLK) 4-88 quadrupler enable (QEN) 4-88 quadrupler select (QSEL) 4-89 SCNTL0 2-25 SCNTL1 2-24, 2-25 SCNTL3 2-36 scratch byte register (SBR) 4-70 register A (SCRATCHA) 4
SEL 2-39 select 2-17 instruction 5-16 with ATN/ 5-20 with SATN/ on a start sequence (WATN) 4-22 selected (SEL) 4-74, 4-77 selection or reselection time-out (STO) 4-75, 4-79 selection response logic test (SLT) 4-87 selection time-out (SEL[3:0]) 4-84 semaphore (SEM) 4-49 serial EEPROM interface 2-50 SERR/ 3-7 SERR/ enable (SE) 4-3 set instruction 5-15, 5-17 set/clear carry 5-20 SACK/ 5-21 shadow register test mode (SRTM) 4-59 SI_O/ status (I_O) 4-39 SID 2-51 SIDL least significant byte full (ILF) 4-42 most si
Ultra SCSI (Cont.) single-ended transfers 20.0 Mbytes (16-bit transfers) quadrupled 40 MHz clock 6-56 20.
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U.S. Distributors by State A. E. Avnet Electronics http://www.hh.avnet.com B. M. Bell Microproducts, Inc. (for HAB’s) http://www.bellmicro.com I. E. Insight Electronics http://www.insight-electronics.com W. E. Wyle Electronics http://www.wyle.com Alabama Daphne I. E. Tel: 334.626.6190 Huntsville A. E. Tel: 256.837.8700 B. M. Tel: 256.705.3559 I. E. Tel: 256.830.1222 W. E. Tel: 800.964.9953 Alaska A. E. Tel: 800.332.8638 Arizona Phoenix A. E. Tel: 480.736.7000 B. M. Tel: 602.267.9551 W. E.
U.S. Distributors by State (Continued) New York Hauppauge I. E. Tel: 516.761.0960 Long Island A. E. Tel: 516.434.7400 W. E. Tel: 800.861.9953 Rochester A. E. Tel: 716.475.9130 I. E. Tel: 716.242.7790 W. E. Tel: 800.319.9953 Smithtown B. M. Tel: 800.543.2008 Syracuse A. E. Tel: 315.449.4927 North Carolina Raleigh A. E. Tel: 919.859.9159 I. E. Tel: 919.873.9922 W. E. Tel: 800.560.9953 North Dakota A. E. Tel: 800.829.0116 W. E. Tel: 612.853.2280 Ohio Cleveland A. E. Tel: 216.498.1100 W. E. Tel: 800.763.
Direct Sales Representatives by State (Component and HAB) E. A. E. L. GRP I. S. ION R. A. SGY Earle Associates Electrodyne - UT Group 2000 Infinity Sales, Inc. ION Associates, Inc. Rathsburg Associates, Inc. Synergy Associates, Inc. Arizona Tempe E. A. Tel: 480.921.3305 California Calabasas I. S. Tel: 818.880.6480 Irvine I. S. Tel: 714.833.0300 San Diego E. A. Tel: 619.278.5441 Illinois Elmhurst R. A. Tel: 630.516.8400 Indiana Cicero R. A. Tel: 317.984.8608 Ligonier R. A. Tel: 219.894.3184 Plainfield R.
Sales Offices and Design Resource Centers LSI Logic Corporation Corporate Headquarters 1551 McCarthy Blvd Milpitas CA 95035 Tel: 408.433.8000 Fax: 408.433.8989 Fort Collins 2001 Danfield Court Fort Collins, CO 80525 Tel: 970.223.5100 Fax: 970.206.5549 New Jersey Red Bank 125 Half Mile Road Suite 200 Red Bank, NJ 07701 Tel: 732.933.2656 Fax: 732.933.2643 NORTH AMERICA Florida Boca Raton Cherry Hill - Mint Technology California Irvine 2255 Glades Road Suite 324A Boca Raton, FL 33431 Tel: 561.989.
Sales Offices and Design Resource Centers (Continued) Korea Seoul LSI Logic Corporation of Korea Ltd 10th Fl., Haesung 1 Bldg. 942, Daechi-dong, Kangnam-ku, Seoul, 135-283 Tel: 82.2.528.3400 Fax: 82.2.528.2250 The Netherlands Eindhoven LSI Logic Europe Ltd World Trade Center Eindhoven Building ‘Rijder’ Bogert 26 5612 LZ Eindhoven Tel: 31.40.265.3580 Fax: 31.40.296.2109 Singapore Singapore LSI Logic Pte Ltd 7 Temasek Boulevard #28-02 Suntec Tower One Singapore 038987 Tel: 65.334.9061 Fax: 65.334.
International Distributors Australia New South Wales Reptechnic Pty Ltd Hong Kong Hong Kong AVT Industrial Ltd 3/36 Bydown Street Neutral Bay, NSW 2089 Unit 608 Tower 1 Cheung Sha Wan Plaza 833 Cheung Sha Wan Road Kowloon, Hong Kong ♦ Tel: 612.9953.9844 Fax: 612.9953.9683 Belgium Acal nv/sa Lozenberg 4 1932 Zaventem Tel: 32.2.7205983 Fax: 32.2.7251014 China Beijing LSI Logic International Services Inc.
