F85K LSI User's Manual

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MICROCOMPUTER MN102H

MN102H75K/F75K/85K/F85K

LSI User’s Manual

Pub.No.22385-011E

Summary of content (338 pages)

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MICROCOMPUTER MN102H MN102H75K/F75K/85K/F85K LSI User’s Manual Pub.No.
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PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names, logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations.
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Contents Contents About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Using This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Register Conventions . . . . . . . . . . . . . .
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Contents 4.5.1 4.5.2 Setting Up an Event Counter Using Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Setting Up an Interval Timer Using Timers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.6 8-Bit Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.7 16-Bit Timer Description . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 6.4.2 6.4.3 6.4.4 6.4.5 Single Channel/Single Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Multiple Channel/Single Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Single Channel/Continuous Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Multiple Channel/Continuous Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . .
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Contents 7.13.3 7.13.4 Controlling Shuttering Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Controlling Line Shuttering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 7.14 7.14.1 7.14.2 7.14.3 Field Detection Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Block Diagram . . . . . .
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Contents 11 I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.2 I/O Port Circuit Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.
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Contents B.4.2 B.4.3 B.4.3.1 B.4.3.2 B.4.4 B.4.4.1 B.4.4.2 B.4.5 B.4.6 B.4.7 B.4.7.1 B.4.7.2 Circuit Requirements for the Target Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Microcontroller Hardware Used in Onboard Serial Programming . . . . . . . . . . . . . . . . . . . . . . . . . 322 Serial Writer Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Serial Writer Interface Block Diagram .
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List of Tables List of Tables 1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-4 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 5-1 5-2 5-3 6-1 6-2 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 8-1 8-2 8-3 8-4 General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block Diagram Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables 8-5 8-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 10-1 11-1 12-1 13-1 13-2 13-3 13-4 13-5 13-6 14-1 A-1 A-2 A-3 B-1 B-2 B-3 B-4 B-5 B-6 B-7 IR Remote Signal Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 HEAMA and 5-/6-Bit Data Pulse Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Pins Used for CCD0 and CCD1 . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures List of Figures 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 Conventional vs. MN102H Series Code Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Three-Stage Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 4-47 4-48 4-49 4-50 4-51 4-52 4-53 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 One-Shot Pulse Output Timing (16-Bit Timers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 External Count Direction Control Timing (16-Bit Timers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 5-12 5-13 5-14 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 Serial Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Master Transmitter Timing in I2C Mode (with ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 7-31 7-32 7-33 7-34 7-35 7-36 7-37 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 10-1 10-2 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 Shuttered Area Setup Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Shutter Movement Setup Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 12-1 12-2 12-3 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 14-1 14-2 14-3 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9 B-10 B-11 B-12 P30/CLH and P33/CLL (Port 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 P34/VREF (Port 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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About This Manual Using This Manual About This Manual This manual is intended for assembly-language programming engineers. It describes the internal configuration and hardware functions of the MN102H75K and MN102H85K microcontrollers. Except when discusssiing differing specifications,this manual refers to the two microcontrollers as a single device : MN102H75K/85K. Using This Manual The chapters in this manual deal with the internal blocks of the MN102H75K/ 85K.
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About This Manual Related Documents Related Documents ■ MN102H Series LSI User Manual (Describes the core hardware.) ■ MN102H Series Instruction Manual (Describes the instruction set.) ■ MN102H Series C Compiler User Manual: Usage Guide (Describes the installation, commands, and options for the C compiler.) ■ MN102H Series C Compiler User Manual: Language Description (Describes the syntax for the C compiler.
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General Description MN102H Series Overview 1 General Description 1.1 MN102H Series Overview The 16-bit MN102H series is the high-speed linear addressing version of the MN10200 series. The new architecture in this series is designed for C-language programming and is based on a detailed analysis of the requirements for embedded applications. From miniaturization to power savings, it provides for a wide range of needs in user systems, surpassing all previous architectures in speed and functionality.
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General Description MN102H Series Features ■ Single-byte basic instruction length The MN102H series has replaced general registers with eight internal CPU registers divided functionally into four address registers (A0 - A3) and four data registers (D0 - D3). The program can address a register pair in four or less bits, and basic instructions such as register-to-register operations and load/store operations occupy only one byte.
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General Description MN102H Series Features ■ Fast interrupt response MN102H series devices can stop executing instructions, even those with long execution cycles, to service interrupts immediately. After an interrupt occurs, the program branches to the interrupt service routine within six cycles or less. The architecture also includes a programmable interrupt handler, which allows you to adjust interrupt servicing speed within the software when necessary, improving real-time control performance.
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General Description MN102H Series Description ■ Outstanding power savings The MN102H series contains separate buses for instructions, data, and peripheral functions, which distributes and reduces load capacitance, dramatically reducing overall power consumption. The series also supports three HALT and STOP modes for even greater power savings. The MN102H series is the flagship product for Panasonic’s new high-performance architecture.
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General Description MN102H Series Description NX: Extension negative flag If the most significant bit of the result of an operation has the value 1, this flag is set; if that bit is 0, this flag is reset. ZX: Extension zero flag If all bits of the result of an operation have the value 0, this flag is set; otherwise it is reset. VF: Overflow flag If the operation causes the sign bit to change in a 16-bit signed number, this flag is set; otherwise it is reset.
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General Description MN102H Series Description ■ Internal registers, memory, and special function registers Program Counter 23 0 The program counter specifies the 24-bit address of the program instruction being executed. PC Address Registers 23 0 The four address registers specify the location of the data in the memory. A3 is assigned as the stack pointer. A0 A1 A2 A3 Data Registers 23 0 The four data registers handle all arithmetic and logic operations.
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General Description MN102H Series Description ■ Address space The memory in the MN102H series is configured as linear address space. The instruction and data areas are not separated, so the basic segments are internal ROM, internal RAM, and special function registers. Figure 1-5 shows the address space for the MN102H75K/85K.The internal ROM contains the instructions and the font data for the on-screen display (OSD), in any location.
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General Description MN102H Series Description ■ Interrupt controller An interrupt controller external to the core controls all nonmaskable and maskable interrupts except reset. There are a maximum of sixteen interrupt classes (class 0 to 15). Each class can have up to four interrupt factors and any of seven priority levels.
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General Description General Specifications 1.
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General Description General Specifications Table 1-1 General Specifications Parameter Specification Timer/counters Four 8-bit timers: ♦ Cascading function (forming 16- or 32-bit timers) ♦ Timer output ♦ Selectable clock source (internal or external) ♦ Serial interface clock generation ♦ Start timing generation for analog-to-digital converter Two 16-bit timers: ♦ Compare/capture registers ♦ Selectable clock source (internal or external) ♦ PWM and one-shot pulse output ♦ Two-phase encoder input (4x or 1x
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General Description Block Diagram 1.
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General Description Block Diagram Table 1-2 Block Diagram Explanation Block Description Clock generator An oscillation circuit connected to an external crystal supplies the clock to all blocks within the CPU. Program counter The program counter generates addresses for queued instructions. Normally it increments based on the sequencer indications, but for branch instructions it is set as the branch head address, and for interrupt servicing, it is set as the result of the ALU operation.
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General Description Pin Descriptions 1.6 Pin Descriptions 1.6.
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General Description Pin Descriptions Notes: P85 NC P56, SBI0, SBD0 P57, SBT0 P60, SDA0 * P86 P61, SCL0 * VDD OSC1 OSC2 VSS P87 P00, RMIN, IRQ0 P01, SDA1 * P02, SCL1 * P03, ADIN0 P04, ADIN1 P05, ADIN2 P06, ADIN3 P07, ADIN4 P70 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 MN102H75K Pin Description 84 1.6.
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General Description Pin Descriptions Table 1-3 Pin Functions Block Power Clocks Reset Interrupts (external) OSD 16-bit (2) Pin Name I/O Pin Count Description VDD I 1 Voltage supply VSS I 2 Ground reference AVDD I 1 Analog voltage supply VDD/VPP I 1 Voltage supply: VDD in mask ROM version and VPP in EEPROM version SYSCLK O 1 System clock output OSC1 I 1 Oscillator input connection (with internal PLL) OSC2 O 1 Oscillator output connection (with internal PLL) OSDXI I 1
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General Description Pin Descriptions Table 1-3 Pin Functions (Continued) Block Pin Name I/O Pin Count Description P00–P07 I/O 8 General-purpose port 0 I/O P10–P17 I/O 8 General-purpose port 1 I/O P20–P27 I/O 8 General-purpose port 2 I/O P30–P37 I/O 8 General-purpose port 3 I/O P40–P47 I/O 8 General-purpose port 4 I/O P50–P57 I/O 8 General-purpose port 5 I/O P60–P61 I/O 2 General-purpose port 6 I/O P70–P77 I/O 8 General-purpose port 7 I/O P80–P87 I/O 8 General-purpose
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General Description Pin Descriptions ■ Considerations for power supply, clock, and reset pins VDD VDD Power Supply AVDD MN102H75K MN102H85K AVSS VSS VSS Note: If the circuit uses the same power supply for digital and analog supplies, connect the pins in the location closest to the power supply. Figure 1-11 Power Supply Wiring OSC1 OSC2 OSC1 OSC2 0.1 µF 4 MHz 4 MHz Oscillation Circuit Note: The capacitance values vary depending on the oscillator.
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General Description Bus Interface 1.7 Bus Interface 1.7.1 Description The bus interface operates in external extension mode. Figure 1-15 provides the memory space for the MCU in this mode.
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General Description Bus Interface 1.7.2 Bus Interface Control Registers The external memory wait register (EXWMD) and memory mode register 1 (MEMMD1) control the bus interface.
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Interrupts Description 2 Interrupts 2.1 Description The most important factor in real-time control is an MCU’s speed in servicing interrupts. The MN102H75K/85K has an extremely fast interrupt response time due to its ability to abort instructions, such as multiply or divide, that require multiple clock cycles. The MN102H75K/85K re-executes an aborted instruction after returning from the interrupt service routine. This section describes the interrupt system in the MN102H75K/85K.
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Interrupts Description Group NMIs MN102H CPU Core Group 0 Group 1 Group 2 Group 3 Group 4 Group 5 Group 6 Group 7 Levels 0 6 Interrupt Vector Watchdog timer Undefined instruction Error interrupt External interrupt 0 External interrupt 1 Priority Level Register Address Class 0 00FC42 (R/W) 00FC44 (R/W) 00FC46 (R/W) Class 1 00FC48 (R/W) 00FC4A (R/W) Group 8 External interrupt 2 Group 9 External interrupt 3 Group 10 Group 11 Class 2 Group 12 External interrupt 4 Group 13 External interrupt 5 Grou
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Interrupts Description g in ss Address 80008 Program e ar dw Interrupt r ha pt Max. 6 cycles In ru er t (9 cl cy ) es e oc pr Handler (preprocessing) jsr (5 ) cycles The interrupt request is Interrupt service deleted in the header routine (Included in the cycle count shown to the left.
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Interrupts Interrupt Setup Examples 2.2 Interrupt Setup Examples 2.2.1 Setting Up an External Pin Interrupt In this example, an interrupt occurs on a falling-edge signal from the IRQ0 (P00) external interrupt pin, and the interrupt priority level is 5. On reset, the external edge setting in the EXTMD register is low (b’00’ = activelow interrupt), and the IQ0IR bit of the IQ0ICL register is 0.
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Interrupts Interrupt Setup Examples 3. Enable interrupts by writing a 1 to the interrupt enable flag (IE) in the PSW and setting the interrupt masking level (IM[2:0]) to 7 (b’111’). Now if a falling edge occurs on IRQ0 (P00), an interrupt will occur. If the CPU accepts the interrupt, the program branches to address x’080008’. ■ The main program normally generates and branches to the interrupt start address. Servicing the interrupt 4.
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Interrupts Interrupt Setup Examples 2.2.2 Setting Up a Watchdog Timer Interrupt In this example, a watchdog timer reset occurs. The watchdog timer starts running after a reset, when the NWDEN flag in the CPU mode register (CPUM) is enabled (set to 0). When the watchdog timer overflows, a nonmaskable interrupt occurs. This means that the watchdog timer must be cleared in the main program. The watchdog timer interrupt is provided for detecting and handling racing.
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Interrupts Interrupt Setup Examples The main program normally generates and branches to the interrupt start address. If the CPU accepts an interrupt, the program branches to address x’080008’. The oscillator delay timer shares the counter for the watchdog timer. The oscillator delay timer is activated when the circuit exits the STOP mode, so the program must clear the WDID flag to 0 prior to entering the STOP mode. It must also reclear WDID after returning to NORMAL mode.
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Interrupts Interrupt Control Registers 2.3 Interrupt Control Registers A control register is assigned to each interrupt vector group. Except for the class 0 registers (WDICR, PIICR, and EIICR), the control registers allow you to enable and set the priority level for interrupt groups. Below is the general format of the registers in class 0 and classes 1 to 11.
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Interrupts Interrupt Control Registers XnICL (System Interrupt) Bit: 7 6 5 4 3 2 1 0 — — — IR — — — ID IR: Interrupt request flag 0: No interrupt requested 1: Interrupt requested ID: Interrupt detect flag 0: Interrupt undetected 1: Interrupt detected The following is an example program setting an interrupt group’s priority level (LV field) and enabling the interrupt group (IE) in the interrupt control register (XnICH). Note that interrupts must be disabled during this routine.
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Interrupts Interrupt Control Registers Table 2-4 Interrupt Control Registers Register Address R/W Description IAGR x’00FC0E’ R WDICR x’00FC42’ R/W PIICR x’00FC44’ R/W EIICR x’00FC46’ R EXTMD x’00FCF8’ R/W External interrupt mode register IQ0ICL IQ0ICH x’00FC48’ x’00FC49’ R/W R/W External interrupt 0 interrupt control register (low) External interrupt 0 interrupt control register (high) IQ1ICL IQ1ICH x’00FC4A’ x’00FC4B’ R/W R/W External interrupt 1 interrupt control register (low)
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Interrupts Interrupt Control Registers Table 2-4 Interrupt Control Registers Register Address R/W Description ADM3ICL ADM3ICH ADM2ICL ADM2ICH ADM1ICL ADM1ICH ADM0ICL ADM0ICH x’00FC78’ x’00FC79’ x’00FC7A’ x’00FC7B’ x’00FC7C’ x’00FC7D’ x’00FC7E’ x’00FC7F’ R/W R/W R/W R/W R/W R/W R/W R/W Address 3 match interrupt control register (low) Address 3 match interrupt control register (high) Address 2 match interrupt control register (low) Address 2 match interrupt control register (high) Address 1 match inte
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Interrupts Interrupt Control Registers IAGR: Accepted Interrupt Group Number Register Bit: x’00FC0E’ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — GN5 GN4 GN3 GN2 GN1 GN0 — — Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R IAGR returns the group number of an accepted interrupt, indicated in the 6-bit GN field.
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Interrupts Interrupt Control Registers PIICR: Undefined Instruction Interrupt Control Register Bit: 7 6 5 4 3 2 1 0 — — — — — — — PIID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W x’00FC44’ PIICR is an 8-bit access register.
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Interrupts Interrupt Control Registers IQ0ICH: External Interrupt 0 Interrupt Control Register (High) Bit: 7 — 6 5 4 IQ0LV2 IQ0LV1 IQ0LV0 3 2 1 0 — — — IQ0IE Reset: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R R R/W x’00FC49’ IQ0ICH sets the priority level for and enables external interrupt 0. It is an 8-bit access register. Use the MOVB instruction to access it. IQ0LV[2:0]: External interrupt 0 interrupt priority level Sets the priority from 0 to 6.
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Interrupts Interrupt Control Registers IQ2ICL: External Interrupt 2 Interrupt Control Register (Low) Bit: 7 6 5 4 3 2 1 0 — — — IQ2IR — — — IQ2ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R x’00FC50’ IQ2ICL requests and verifies interrupt requests for external interrupt 2. It is an 8-bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers IQ3ICH: External Interrupt 3 Interrupt Control Register (High) Bit: 7 6 5 4 3 2 1 0 — — — — — — — IQ3IE Reset: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W x’00FC53’ IQ3ICH enables external interrupt 3. It is an 8-bit access register. Use the MOVB instruction to access it. The priority level for external interrupt 3 is written to the IQ2LV[2:0] field of the IQ2ICH register.
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Interrupts Interrupt Control Registers IQ5ICL: External Interrupt 5 Interrupt Control Register (Low) Bit: 7 6 5 4 3 2 1 0 — — — IQ5IR — — — IQ5ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R x’00FC5A’ IQ5ICL requests and verifies interrupt requests for external interrupt 5. It is an 8-bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers TM4CBICH: Timer 4 Compare/Capture B Interrupt Control Register (High)x’00FC61’ Bit: 7 — 6 5 4 TM4CB TM4CB TM4CB LV2 LV1 LV0 3 2 — — 1 0 — TM4CB IE Reset: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R R R/W TM4CBICH sets the priority level for and enables timer 4 compare/capture B interrupts. It is an 8-bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers TM4UDICL: Timer 4 Underflow Interrupt Control Register (Low) Bit: 7 6 5 4 3 2 1 0 — — — TM4UD IR — — — TM4UD ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R x’00FC64’ TM4UDICL detects and requests timer 4 underflow interrupts. It is an 8bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers VBIICH: VBI (1) Interrupt Control Register (High) Bit: 7 6 5 4 3 2 1 0 — — — — — — — VBI IE Reset: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W x’00FC67’ VBIICH enables VBI (1) interrupts. It is an 8-bit access register. Use the MOVB instruction to access it. The priority level for VBI (1) interrupts is written to the TM4CBLV[2:0] field of the TM4CBICH register.
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Interrupts Interrupt Control Registers TM5CAICL: Timer 5 Compare/Capture A Interrupt Control Register (Low) x’00FC6A’ Bit: 7 — 6 — 5 4 — TM5CA IR 3 2 — — 1 0 — TM5CA ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R TM5CAICL detects and requests timer 5 compare/capture interrupts. It is an 8-bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers TM5UDICH: Timer 5 Underflow Interrupt Control Register (High) Bit: 7 6 5 4 3 2 1 0 — — — — — — — TM5UD IE Reset: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W x’00FC6D’ TM5UDICH enables timer 5 underflow interrupts. It is an 8-bit access register. Use the MOVB instruction to access it. The priority level for timer 5 underflow interrupts is written to the TM5CBLV[2:0] field of the TM5CBICH register.
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Interrupts Interrupt Control Registers TM2UDICL: Timer 2 Underflow Interrupt Control Register (Low) Bit: 7 6 5 4 3 2 1 0 — — — TM2UD IR — — — TM2UD ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R x’00FC70’ TM2UDICL register detects and requests timer 2 underflow interrupts. It is an 8-bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers TM1UDICH: Timer 1 Underflow Interrupt Control Register (High) Bit: 7 6 5 4 3 2 1 0 — — — — — — — TM1UD IE Reset: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W x’00FC73’ TM1UDICH enables timer 1 underflow interrupts. It is an 8-bit access register. Use the MOVB instruction to access it. The priority level for timer 1 underflow interrupts is written to the TM2UDLV[2:0] field of the TM2UDICH register.
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Interrupts Interrupt Control Registers RMCICL: Remote Signal Receive Interrupt Control Register (Low) Bit: 7 6 5 4 3 2 1 0 — — — RMC IR — — — RMC ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R x’00FC76’ RMCICL detects and requests remote signal receive interrupts. It is an 8bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers ADM3ICH: Address 3 Match Interrupt Control Register (High) Bit: 7 6 5 4 3 2 1 0 — ADM3 LV2 ADM3 LV1 ADM3 LV0 — — — ADM3 IE Reset: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R R R/W x’00FC79’ ADM3ICH sets the priority level for and enables address match 3 interrupts. It is an 8-bit access register. Use the MOVB instruction to access it. ADM3LV[2:0]: Address match 3 interrupt priority level Sets the priority from 0 to 6.
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Interrupts Interrupt Control Registers ADM1ICL: Address 1 Match Interrupt Control Register (Low) Bit: 7 6 5 4 3 2 1 0 — — — ADM1 IR — — — ADM1 ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R x’00FC7C’ ADM1ICL detects and requests address match 1 interrupts. It is an 8-bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers ADM0ICH: Address 0 Match Interrupt Control Register (High) Bit: 7 6 5 4 3 2 1 0 — — — — — — — ADM0 IE Reset: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W x’00FC7F’ ADM0ICH enables address match 0 interrupts. It is an 8-bit access register. Use the MOVB instruction to access it. The priority level for address match 0 interrupts is written to the ADM3LV[2:0] field of the ADM3ICH register.
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Interrupts Interrupt Control Registers SCT0ICL: Serial 0 Transmission End Interrupt Control Register (Low) x’00FC82’ Bit: 7 — 6 — 5 4 — SCT0 IR 3 2 — — 1 0 — SCT0 ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R SCT0ICL detects and requests serial 0 transmission end interrupts. It is an 8-bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers SCR0ICH: Serial 0 Reception End Interrupt Control Register (High) Bit: 7 6 5 4 3 2 1 0 — — — — — — — SCR0 IE Reset: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W x’00FC85’ SCR0ICH enables serial 0 reception end interrupts. It is an 8-bit access register. Use the MOVB instruction to access it. The priority level for serial 0 reception end interrupts is written to the ANLV[2:0] field of the ANICH register.
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Interrupts Interrupt Control Registers VBIVWICL: VBIVSYNC (2) Interrupt Control Register (Low) Bit: 7 6 5 4 3 2 1 0 — — — VBIVW IR — — — VBIVW ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R x’00FC8A’ VBIVWICL detects and requests VBIVSYNC (2) interrupts. It is an 8-bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers TM3UDICH: Timer 3 Underflow Interrupt Control Register (High) Bit: 7 6 5 4 3 2 1 0 — — — — — — — TM3UD IE Reset: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W x’00FC8D’ TM3UDICH enables timer 3 underflow interrupts. It is an 8-bit access register. Use the MOVB instruction to access it. The priority level for timer 3 underflow interrupts is written to the VBIVLV[2:0] field of the VBIVICH register.
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Interrupts Interrupt Control Registers OSDCICL: OSD (Text) Interrupt Control Register (Low) Bit: 7 6 5 4 3 2 1 0 — — — OSDC IR — — — OSDC ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R x’00FC92’ OSDCICL detects and requests OSD (text) interrupts. It is an 8-bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers SCT1ICH: Serial 1 Transmission End Interrupt Control Register (High) x’00FC99’ Bit: 7 6 5 4 — SCT1 LV2 SCT1 LV1 SCT1 LV0 3 2 — — 1 0 — SCT1 IE Reset: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R R R/W SCT1ICH sets the priority level for and enables serial 1 transmission end interrupts. It is an 8-bit access register. Use the MOVB instruction to access it.
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Interrupts Interrupt Control Registers I2CICL: I2C Interrupt Control Register (Low) Bit: x’00FC9C’ 7 6 5 4 3 2 1 0 — — — I2C IR — — — I2C ID Reset: 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R I2CICL detects and requests I2C interrupts. It is an 8-bit access register. Use the MOVB instruction to access it.
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Low-Power Modes CPU Modes 3 Low-Power Modes The MN102H75K/85K provides two ways to reduce power consumption, controlling CPU operating and standby modes to cut overall consumption and shutting down unused functions by stopping the system clock supplied to them. 3.1 CPU Modes 3.1.1 Description The MN102H75K/85K has two CPU operating modes, NORMAL and SLOW, and two CPU standby modes, HALT and STOP. Effective use of these modes can significantly reduce power consumption.
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Low-Power Modes CPU Modes 3.1.2 The MN102H75K/85K recovers from power up and reset in SLOW mode. For normal operation, the program must switch the MCU from SLOW to NORMAL mode. Exiting from SLOW Mode to NORMAL Mode The MN102H75K/85K contains a PLL circuit that, in NORMAL mode, multiplies the clock input through the OSC1 and OSC2 pins by 12, divides the signal by 2, then sends the resulting clock to the CPU. (See figure 3-2.) The MCU starts in SLOW mode on power up and on recovery from a reset.
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Low-Power Modes CPU Modes 3.1.3 ■ Notes on Invoking and Exiting STOP and HALT Modes When invoking STOP and HALT modes... To reduce power consumption before invoking the STOP or HALT mode, stop current flow from output pins and stabilize the input level of input pins. For output pins, either match the output level to the external level or set the pin to input. For input pins, ensure that the external level is fixed.
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Low-Power Modes Turning Individual Functions On and Off 3.2 You cannot set the PLL function control bit during NORMAL mode. You must set it from the SLOW mode. Turning Individual Functions On and Off The MN102H75K/85K allows you to turn each peripheral function on or off through writing to the registers. You can significantly reduce power consumption by turning off unused functions. Table 3-1 shows the register bits controlling on and off for each function block.
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Low-Power Modes CPU Control Register 3.3 CPU Control Register CPUM: CPU Mode Control Register Bit: 15 14 NW DEN — 13 — 12 11 — — 10 9 — x’00FC00’ 8 — — 7 — 6 — 5 4 3 — OSC ID 2 1 0 STOP HALT OSC1 OSC0 Reset: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R R R R R R R R R R R R/W R/W R/W R/W This register controls the invoking of all of the CPU modes.
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Timers 8-Bit Timer Description 4 Timers 4.1 8-Bit Timer Description The MN102H75K/85K contains four 8-bit timers that can serve as interval timers, event timer/counters, clock generators (divide-by-2 output of the underflow), reference clocks for the serial interfaces, or start timers for A/D conversions. The clock source can be the internal clock (oscillator frequency divided by 2) or the external clock (1/4 or less the oscillator frequency input). A timer interrupt is generated by a timer underflow.
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Timers 8-Bit Timer Features 4.
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Timers 8-Bit Timer Block Diagrams 4.
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Timers 8-Bit Timer Block Diagrams Data bus 8 8 8 (FE12) Timer 2 base register TM2BR Reload Load 8 (FE22) TM2S0 TM2S1 TM2LD TM2EN TM2MD (FE02) Timer 2 binary counter TM2BC Underflow Timer 2 underflow interrupt Underflow Timer 3 underflow interrupt Count BOSC/4 0 BOSC/256 1 Cascade from timer 1 2 3 BOSC/512 Multiplexer Figure 4-5 Timer 2 Block Diagram Data bus 8 8 8 (FE13) Timer 3 base register TM3BR Reload Load 8 (FE23) TM3S0 TM3S1 TM3LD TM3EN TM3MD (FE03) Timer 2 binar
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Timers 8-Bit Timer Timing 4.
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Timers 8-Bit Timer Setup Examples 4.5 8-Bit Timer Setup Examples 4.5.1 Setting Up an Event Counter Using Timer 0 In this example, timer 0 generates an underflow interrupt on the fourth rising edge of the TM0IO signal. The event counter continues to operate during STOP mode. In all modes but STOP, the TMnIO signal input is synchronized to BOSC. In STOP mode, the timer counts TMnIO signal directly. When an interrupt occurs, the CPU returns to NORMAL mode after the oscillator stabilization wait.
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Timers 8-Bit Timer Setup Examples TM0UDICL (example) Bit: Setting: x’00FC74’ 7 6 5 4 3 2 1 0 — — — TM0UD IR — — — TM0UD ID 0 0 0 0 0 0 0 0 TM0UDICH (example) Bit: Setting: x’00FC75’ 7 6 5 4 3 2 1 0 — — — — — — — TM0UD IE 0 0 0 0 0 0 0 1 4. Set the divide-by ratio for timer 0. Since the timer will count 4 TM0IO cycles, write x’03’ to the timer 0 base register (TM0BR). (The valid range for TM0BR is 0 to 255.
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Timers 8-Bit Timer Setup Examples 4.5.2 Setting Up an Interval Timer Using Timers 1 and 2 In this example, timers 1 and 2 are cascaded to divide BOSC/4 by 60,000 and generate an underflow interrupt.
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Timers 8-Bit Timer Setup Examples TM2UDICH (example) Bit: 7 6 4 TM2UD TM2UD TM2UD LV2 LV1 LV0 — Setting: 5 0 1 0 0 x’00FC71’ 3 2 1 0 — — — TM2UD IE 0 0 0 1 TM2UDICL (example) Bit: Setting: x’00FC70’ 7 6 5 4 3 2 1 0 — — — TM2UD IR — — — TM2UD ID 0 0 0 0 0 0 0 0 TM1UDICH (example) Bit: Setting: x’00FC73’ 7 6 5 4 3 2 1 0 — — — — — — — TM0UD IE 0 0 0 0 0 0 0 0 TM1UDICL (example) Bit: Setting: x’00FC72’ 7 6 5 4 3 2 1 0 — —
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Timers 8-Bit Timer Setup Examples TM2MD (example) Bit: 6 5 4 3 2 1 0 TM2 EN TM2 LD — — — — TM2 S1 TM2 S0 0 1 0 0 0 0 1 0 Setting: In the bank and linear addressing versions of the MN102 series, it was necessary to set TM0EN and TM0LD to 0 between steps 4 and 5, to ensure stable operation. This is unnecessary in the high-speed linear addressing version.
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Timers 8-Bit Timer Control Registers 4.6 8-Bit Timer Control Registers Table 4-2 shows the registers used to control the 8-bit timers. A binary counter (TMnBC), a time base counter (TMnBR), and a timer mode register (TMnMD) is associated with each 8-bit timer.
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Timers 16-Bit Timer Description 4.7 16-Bit Timer Description The MN102H75K/85K contains two 16-bit up/down timers, timers 5 and 6. Associated with each timer are two compare/capture registers that can capture and compare the up/down counter values, generate PWM signals, and generate interrupts. The PWM function has a double buffering mode that causes cycle and transition changes to occur at the beginning of the next clock cycle.
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Timers 16-Bit Timer Features 4.
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Timers 16-Bit Timer Block Diagrams 16-Bit Timer Block Diagrams TM4IC pin Timer 0 underflow Timer 1 underflow TM4IB pin BOSC/4 [S] Selector 4.
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Timers 16-Bit Timer Timing New value written to CCRB BC value Change reflected in next clock cycle CA CB Time TMnIOA TMnOA Figure 4-18 Single-Phase PWM Output Timing with Data Change (16-Bit Timers) BC value CA CB Time TMnOA TMnOB Figure 4-19 Two-Phase PWM Output Timing (16-Bit Timers) BC value CA Time TMnIB TMnOA Figure 4-20 One-Shot Pulse Output Timing (16-Bit Timers) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 91 Panasonic
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Timers 16-Bit Timer Timing BC value CA Time TMnIB TMnIA Figure 4-21 External Count Direction Control Timing (16-Bit Timers) BC value Time TMnIB Figure 4-22 Event Timer Input Timing (16-Bit Timers) BC value FFFF Time TMnIB TMnIA 0033 (Example) TMnCA 5A87 (Example) TMnCB Figure 4-23 Single-Phase Capture Input Timing (16-Bit Timers) Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual 92 Panasonic
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Timers 16-Bit Timer Timing BC value FFFF Time TMnIB TMnIA 0033 (Example) TMnCA 5A87 (Example) TMnCB Figure 4-24 Two-Phase Capture Input Timing (16-Bit Timers) BC value Time TMnIA TMnIB Figure 4-25 Two-Phase 4x Encoder Timing (16-Bit Timers) BC value Time TMnIA TMnIB Figure 4-26 Two-Phase 1x Encoder Timing (16-Bit Timers) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 93 Panasonic
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Timers 16-Bit Timer Setup Examples 4.11 16-Bit Timer Setup Examples 4.11.1 Setting Up an Event Counter Using Timer 4 In this example, timer 4 counts the TM4IB input signal (BOSC/4 = 6 MHz or less) and generates an interrupt on the second and fifth cycles. TM4IB P2 CORE ROM, RAM P4 P6 Interrupts Bus Controller P5 Timers 0-3 Serial I/Fs Timers 4-5 ADC A. Chip Level Timer 4 (BOSC/4) TM4BC up TM4CA T Controller TM4IB Q TM4CAX R Q S (TM4OA) TM4CB T Q TM4CBX B.
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Timers 16-Bit Timer Setup Examples TM4CA (example) Bit: 15 14 13 TM4 TM4 TM4 CA15 CA14 CA13 Setting: 0 3. 0 0 12 TM4 CA12 0 x’00FE84’ 11 10 TM4 TM4 CA11 CA10 0 0 9 8 7 6 5 4 3 2 1 0 TM4 CA9 TM4 CA8 TM4 CA7 TM4 CA6 TM4 CA5 TM4 CA4 TM4 CA3 TM4 CA2 TM4 CA1 TM4 CA0 0 0 0 0 0 0 0 1 0 0 Set the phase difference for timer 4. For a 2-cycle phase difference, write x’0001’ to timer 4 compare/capture register B (TM4CB). (The valid range is -1 ≤ TM4CB < the TM4CA value.
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Timers 16-Bit Timer Setup Examples 4.11.2 Setting Up a Single-Phase PWM Output Signal Using Timer 4 In this example, timer 4 is used to divide BOSC by 5 and generate a five-cycle, single-phase PWM signal. The duty of this signal is 2:3. To accomplish this, the program must load the divide-by ratio of 5 (actual setting: 4) into compare/ capture register A and a cycle count of 2 (actual setting: 1) into compare/capture register B.
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Timers 16-Bit Timer Setup Examples P2DIR (example) Bit: 6 5 4 3 2 1 0 P2 DIR7 P2 DIR6 P2 DIR5 P2 DIR4 P2 DIR3 P2 DIR2 P2 DIR1 P2 DIR0 0 1 0 0 0 0 0 0 Setting: ■ To set up timer 4: 1. Use the MOV instruction for this setup and only use 16-bit write operations. This step stops the TM4BC count and clears both TM4BC and the S-R flip-flop to 0. x’00FFE2’ 7 Set the operating mode in the timer 4 mode register (TM4MD). Disable timer 4 counting and interrupts. Select up counting.
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Timers 16-Bit Timer Setup Examples 6. Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0. This enables TM4BC and the S-R flip-flop. This step ensures stable operation. If it is omitted, the binary counter may not count the first cycle. Do not change any other operating modes during this step. 7. Set TM4NLD and TM4EN to 1. This starts the timer. Counting begins at the start of the next cycle. Timer 4 can output a single-phase PWM signal at any duty. You must select up counting.
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Timers 16-Bit Timer Setup Examples Figure 4-30 below shows the output waveforms for TM4OA. Both A and B interrupts can occur, but B interrupts can only occur if the TM4CB setting is from 0 to less than TM4CA. This is because when TM4CB ≤ TM4CA, TM4BC never matches TM4CB.
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Timers 16-Bit Timer Setup Examples Two potential types of errors are inherent with PWM output. First, because of the circuit configuration, direction errors can occur. The output circuit is configured with T flip-flops, so that even if one transition is missed, the 1s and 0s can reverse direction. Timers 4 and 5 contain an S-R flip-flop to prevent this type of error.
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Timers 16-Bit Timer Setup Examples 4.11.3 Setting Up a Two-Phase PWM Output Signal Using Timer 4 In this example, timer 4 is used to divide timer 0 underflow by 5 and generate a five-cycle, two-phase PWM signal. The phase difference of this signal is 2 cycles. To accomplish this, the program must load the divide-by ratio of 5 (actual setting: 4) into compare/capture register A and a cycle count of 2 (actual setting: 1) into compare/capture register B.
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Timers 16-Bit Timer Setup Examples P2DIR (example) Bit: 6 5 4 3 2 1 0 P2 DIR7 P2 DIR6 P2 DIR5 P2 DIR4 P2 DIR3 P2 DIR2 P2 DIR1 P2 DIR0 0 1 1 0 0 0 0 0 Setting: ■ x’00FFE2’ 7 To set up timer 0: 1. Disable timer 0 counting in the timer 0 mode register (TM0MD). This step is unnecessary immediately after a reset, since TM0MD resets to 0. TM0MD (example) Bit: 7 6 TM0 EN TM0 LD — — 0 0 0 0 Setting: 2.
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Timers 16-Bit Timer Setup Examples ■ To set up timer 4: 1. Use the MOV instruction for this setup and only use 16-bit write operations. This step stops the TM4BC count and clears both TM4BC and the S-R flip-flop to 0. Set the operating mode in the timer 4 mode register (TM4MD). Disable timer 4 counting and interrupts. Select up counting. Select timer 0 underflows as the clock source. TM4MD (example) Bit: 15 14 TM4 EN TM4 NLD 0 0 Setting: 2.
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Timers 16-Bit Timer Setup Examples 6. Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0. This enables TM4BC and the S-R flip-flop. This step ensures stable operation. If it is omitted, the binary counter may not count the first cycle. Do not change any other operating modes during this step. 7. Set TM4NLD and TM4EN to 1. This starts the timer. Counting begins at the start of the next cycle. Timer 4 can output a two-phase PWM signal with any phase difference.
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Timers 16-Bit Timer Setup Examples With PWM output, the duty cycle can change dynamically, which can cause the PWM waveform to skip a pulse (see the single buffering section of figure 4-34 below). To prevent these misses, timers 4 and 5 provide a double-buffer mode. In this mode, no matter what the timing of a TMnCB change, the duty change does not occur until the beginning of the next cycle, and no signals are lost.
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Timers 16-Bit Timer Setup Examples 4.11.4 Setting Up a Single-Phase Capture Input Using Timer 4 In this example, timer 4 is used to divide BOSC/4 by 65,536 and measure how long the TM4IA input signal stays high. An interrupt occurs on capture B and the software calculates the number of cycles by subtracting the contents of TMnCA from the contents of TMnCB. TM4IA P3 CORE ROM, RAM P4 P6 Interrupts Bus Controller P5 Timers 0-3 Serial I/Fs Timers 4-5 ADC P2 A.
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Timers 16-Bit Timer Setup Examples change any other operating modes during this step. When TM4MD[1:0] = b’10’ (during capture), TM4CA and TM4CB become read-only registers. To write to TM4CA or TM4CB, you must first set TM4MD[1:0] = b’00’. 3. ■ To enable timer 4 capture B interrupts: Cancel all existing interrupt requests. Next, set the interrupt priority level in the TM4CBLV[2:0] bits of the TM4CBICH register (levels 0 to 6), set the TM4BIE bit to 1, and set the TM4BIR bit of TM4CBICL to 0.
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Timers 16-Bit Timer Setup Examples 4.11.5 Setting Up a Two-Phase Capture Input Using Timer 4 In this example, timer 4 is used to divide the timer 0 underflow by 65,536 and measure the number of cycles from the rising edge of the TM4IA input signal to the rising edge of the TM4IB input signal. An interrupt occurs on capture B and the software calculates the number of cycles by subtracting the contents of TMnCA from the contents of TMnCB.
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Timers 16-Bit Timer Setup Examples TM0BR (example) Bit: 6 5 4 3 2 1 0 TM0 BR7 TM0 BR6 TM0 BR5 TM0 BR4 TM0 BR3 TM0 BR2 TM0 BR1 TM0 BR0 0 0 0 0 0 0 0 1 Setting: 3. Do not change the clock source once you select it. Selecting the clock source while you set up the count operation control will corrupt the value in the binary counter.
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Timers 16-Bit Timer Setup Examples ■ Ignore the flags when calculating the signal width, even when TM3CA is the larger value. To service the interrupts and calculate the signal width: 1. Run the interrupt service routine. The routine must determine the interrupt group, then clear the interrupt request flag. 2. Calculate the number of cycles the TM4IA signal stays high. Save the contents of TM4CA and TM4CB to the data registers, then subtract the contents of TM4CA from the contents of TM4CB.
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Timers 16-Bit Timer Setup Examples 4.11.6 Setting Up a 4x Two-Phase Encoder Input Using Timer 5 In this example, timer 5 inputs a 4x two-phase encoded signal that makes it count up and down. An interrupt occurs when the counter reaches a preset value. TM5IA TM5IB P2 CORE ROM, RAM P3 P6 Interrupts Bus Controller P5 Timers 0-3 Serial I/Fs Timers 4-5 ADC P4 A. Chip Level Timer 5 TM5BC up/down TM5CA TM5IA Interrupt B Controller T Q R Q S TM5CB TM5IB T Q B.
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Timers 16-Bit Timer Setup Examples ■ To set up timer 5: 1. Use the MOV instruction for this setup and only use 16-bit write operations. TM5MD (example) Bit: This step stops the TM5BC count and clears both TM5BC and the S-R flip-flop to 0. Set the operating mode in the timer 5 mode register (TM5MD). Disable timer 5 counting and interrupts. The up/down count bit is ignored in this instance. Set the TM5NLP bit to 1 to select looped counting from 0 to the value in TM5CA.
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Timers 16-Bit Timer Setup Examples ■ To service the interrupts: Run the interrupt service routine. The routine must determine the interrupt group, then clear the interrupt request flag. Timer 5 can input a two-phase encoder signal. Timer 5 does not operate in STOP mode, when BOSC is off. If you use an external clock, it must be synchronized to BOSC. Table 4-4 shows the count direction for the timing diagram in figure 4-42.
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Timers 16-Bit Timer Setup Examples 4.11.7 Setting Up a 1x Two-Phase Encoder Input Using Timer 5 In this example, timer 5 inputs a 1x two-phase encoded signal that makes it count up and down. An interrupt occurs when the counter reaches a preset value. TM5IA TM5IB P2 CORE ROM, RAM P3 P6 Interrupts Bus Controller P5 Timers 0-3 Serial I/Fs Timers 4-5 ADC P4 A. Chip Level Timer 5 TM5BC up/down TM5CA TM5IA Interrupt B Controller T Q R Q S TM5CB TM5IB T Q B.
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Timers 16-Bit Timer Setup Examples ■ To set up timer 5: 1. Use the MOV instruction for this setup and only use 16-bit write operations. TM5MD (example) Bit: This step stops the TM5BC count and clears both TM5BC and the S-R flip-flop to 0. Set the operating mode in the timer 5 mode register (TM5MD). Disable timer 5 counting and interrupts. The up/down count bit is ignored in this instance. Set the TM5NLP bit to 1 to select looped counting from 0 to the value in TM5CA.
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Timers 16-Bit Timer Setup Examples ■ To service the interrupts: Run the interrupt service routine. The routine must determine the interrupt group, then clear the interrupt request flag. Timer 5 can input a two-phase encoder signal. Timer 5 does not operate in STOP mode, when BOSC is off. If you use an external clock, it must be synchronized to BOSC. Table 4-5 shows the count direction for the timing diagram in figure 4-46.
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Timers 16-Bit Timer Setup Examples 4.11.8 Setting Up a One-Shot Pulse Output Using Timer 5 In this example, timer 5 outputs a one-shot pulse. The pulse width is two clock cycles. P2 CORE ROM, RAM P3 P6 Interrupts Bus Controller P5 Timers 0-3 Serial I/Fs Timers 4-5 ADC TM5OA TM5IB P4 A. Chip Level Timer 5 BOSC/4 TM5BC up/down TM5CA T Controller TM5IB Q TM5CAX R Q S TM5OA TM5CB T Q TM5CBX B.
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Timers 16-Bit Timer Setup Examples ■ To set up timer 5: 1. Use the MOV instruction for this setup and only use 16-bit write operations. This step stops the TM5BC count and clears both TM5BC and the S-R flip-flop to 0. Set the operating mode in the timer 5 mode register (TM5MD). Disable timer 5 counting and interrupts. Select up counting. Select BOSC/4 as the clock source. TM5MD (example) Bit: 15 14 TM5 EN TM5 NLD 0 0 Setting: 2.
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Timers 16-Bit Timer Setup Examples Timer 5 can output a one-shot pulse. Timer 5 does not operate in STOP mode, when BOSC is off. If you use an external clock, it must be synchronized to BOSC. Figure 4-48 shows an example timing diagram for one-shot pulse output. On the falling edge of TM5IB, the TM5EN flag is set, and counting begins at the start of the next cycle. Before the count starts, TM5BC is 0, the initial TM5OA output value is 0, and the R5 (reset) and S5 (set) signals are not asserted.
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Timers 16-Bit Timer Setup Examples 4.11.9 Setting Up an External Count Direction Controller Using Timer 5 In this example, timer 5 counts BOSC/4 and the TM5IA pin controls the count direction (up or down). An interrupt occurs when the counter reaches a preset value. TM5IA P2 CORE ROM, RAM P3 P6 Interrupts Bus Controller P5 Timers 0-3 Serial I/Fs Timers 4-5 ADC P4 A. Chip Level Timer 5 BOSC/4 TM5BC up/down TM5CA TM5IA Controller T Q R Q S TM5CB Interrupt B T Q B.
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Timers 16-Bit Timer Setup Examples ■ To set up timer 5: 1. Use the MOV instruction for this setup and only use 16-bit write operations. TM5MD (example) Bit: This step stops the TM5BC count and clears both TM5BC and the S-R flip-flop to 0. Set the operating mode in the timer 5 mode register (TM5MD). Disable timer 5 counting and interrupts. Set the TM5UD[1:0] bits to b’10’, so that the count direction is up when the TM5IA signal is high and down when the TM5IA signal is low.
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Timers 16-Bit Timer Setup Examples ■ To service the interrupts: Run the interrupt service routine. The routine must determine the interrupt group, then clear the interrupt request flag. Either the TM5IA or TM5IB signal can control the timer 5 count direction. The count direction is determined at the opposite edge from the count edge (at the source clock transition occurring in the middle of the count cycle.). Timer 5 does not operate in STOP mode, when BOSC is off.
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Timers 16-Bit Timer Setup Examples 4.11.10 Setting Up External Reset Control Using Timer 5 In this example, timer 5 is reset by an external signal while counting up. TM5IC P2 CORE ROM, RAM P3 P6 Interrupts Bus Controller P5 Timers 0-3 Serial I/Fs Timers 4-5 ADC P4 A. Chip Level Timer 5 BOSC/4 TM5BC reset TM5CA Controller T Q R Q S TM5CB TM5IC T Q B. Block Level Figure 4-52 Block Diagram of External Reset Control Using Timer 5 ■ To set up timer 5: 1.
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Timers 16-Bit Timer Setup Examples TM5CA (example) Bit: 15 14 13 12 TM5 TM5 TM5 CA15 CA14 CA13 Setting: 0 0 TM5 CA12 0 1 x’00FE94’ 11 10 TM5 TM5 CA11 CA10 1 1 9 8 7 6 5 4 3 2 1 0 TM5 CA9 TM5 CA8 TM5 CA7 TM5 CA6 TM5 CA5 TM5 CA4 TM5 CA3 TM5 CA2 TM5 CA1 TM5 CA0 1 1 1 1 1 1 1 1 1 1 3. Set the TM5NLD bit of the TM5MD register to 1 and the TM5EN bit to 0. This enables TM5BC and the S-R flip-flop. This step ensures stable operation.
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Timers 16-Bit Timer Control Registers 4.12 16-Bit Timer Control Registers Table 4-6 shows the registers used to control the 16-bit timers. A binary counter (TMnBC), a compare/capture register A (TMnCA), a compare/capture register B (TMnCB), and a timer mode register (TMnMD) is associated with each 16-bit timer.
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Timers 16-Bit Timer Control Registers TM4MD/TM5MD: Timer n Mode Register Bit: 15 14 13 TMn EN TMn NLD — x’00FE80’/x’00FE90’ 12 11 10 9 8 7 6 5 4 3 2 1 0 — TMn UD1 TMn UD0 TMn TGE TMn ONE TMn MD1 TMn MD0 TMn ECLR TMn LP TMn ASEL TMn S2 TMn S1 TMn S0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TMnEN: TMnBC count 0: Disable 1: Enable TMnNLD: TMnBC, T flip-flop, and S-R flip-flop ope
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Serial Interfaces Description 5 Serial Interfaces 5.1 Description The MN102H75K/85K contains two general-purpose serial interfaces with synchronous serial, UART, and I2C modes. The maximum baud rate in synchronous serial mode is 12 Mbps. In UART mode, the maximum baud rate is 375,000 bps, when BOSC = 24 MHz.
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Serial Interfaces Connecting the Serial Interfaces 5.3 Connecting the Serial Interfaces Figures 5-2, 5-3, and 5-4 illustrate six different methods of connecting the serial interface. 5.3.1 Synchronous Serial Mode Connections SBI SBI SBT SBT A. Simplex Connection SBO SBO SBI SBI SBT SBT Transmit/receive SBO Transmit/receive SBO Receive Figure 5-2 shows serial port connections for either simplex or full-duplex synchronous serial transfers.
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Serial Interfaces UART Mode Baud Rates 5.4 UART Mode Baud Rates In UART mode, the serial interface transfer clock is set to 16 times the baud rate clock. The expression below is the formula for calculating the baud rate for the UART mode. Table 5-2 shows the baud rate settings when BOSC = 24 MHz.
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Serial Interfaces Serial Interface Timing Rx SBI b0 b1 b2 b3 b4 b5 b6 b7 PTY SBT RXBUSY Rx interrupt RXA (1 when Rx data in) Data read Figure 5-6 Synchronous Serial Reception Timing 5.5.2 UART Mode Timing In these timing charts, the character length is 8 bits, the parity is none, and the stop bit is 2-bit.
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Serial Interfaces Serial Interface Setup Examples 5.6 Serial Interface Setup Examples 5.6.1 Setting Up UART Transmission Using Serial Interface 0 This example illustrates serial transmission in the UART mode with the following settings: You must use an 8-bit timer to set the transfer clock. See section 5.6.3, “Setting Up the Serial Interface Clock,” on page 135, for an example setup.
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Serial Interfaces Serial Interface Setup Examples ■ To set up serial interface 0: 1. Configure the transmission settings in the serial port 0 control register (SC0CTR). Since the transfer clock is timer 0 divided by 8, select timer 0 underflow x 1/8 as the serial port 0 clock source. Select UART mode, odd parity, 2-bit stop bit, 8-bit data length, and LSB-first output. Also set the SC0REN and SC0TEN flags to 0, disabling transmission and reception.
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Serial Interfaces Serial Interface Setup Examples ■ Transmission sequence: 1. Write the first data byte to SC0TRB. Once this data is in the register, transmission begins, synchronized to timer 0. 2. When an interrupt occurs, the program branches to the interrupt service routine. The routine must determine the interrupt group, then clear the interrupt request flag. 3. Write the next data byte to SC0TRB.
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Serial Interfaces Serial Interface Setup Examples 5.6.2 Setting Up Synchronous Serial Reception Using Serial Interface 0 This example illustrates serial reception in the synchronous serial mode with the following settings: ♦ LSB first ♦ 8-bit character length ♦ Odd parity When a reception end interrupt occurs, the CPU reads the data byte. ■ To set up the input port: Set the P5DIR7 bit of the port 5 I/O control register (P5DIR) to 0. This sets the SBT0 pin to input.
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Serial Interfaces Serial Interface Setup Examples 5.6.3 Setting Up the Serial Interface Clock This example demonstrates how to set up a 19,200 bps transfer clock for the UART interface by using timer 1 to divide BOSC/4 by 39. The example uses the following settings: ♦ BOSC = 24 MHz ♦ Clock source = timer 1 underflow x 1/8 ♦ Transfer clock = baud rate x 8 The serial interface determines the baud rate from the 8-bit underflow.
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Serial Interfaces Serial Interface Setup Examples 3. Do not change the clock source once you select it. Selecting the clock source while you set up the count operation control will corrupt the value in the binary counter. In the bank and linear addressing versions of the MN102 series, it was necessary to set TM1EN and TM1LD to 0 between steps 3 and 4, to ensure stable operation. This is unnecessary in the high-speed linear addressing version. Set the TM1LD bit of the TM1MD register to 1.
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Serial Interfaces Serial Interface Setup Examples Setting Up I 2 C Transmission Using Serial Interface 0 5.6.4 This example illustrates the microcontroller as a master transmitter in the I2C mode, using the SBO0 and SBT0 pins. ■ I2C mode requires open-drain pins. To set this up, set the ODASCI0 bit of PCNT0 (x’00FF90’) to 1. In addition, set the P5PUP7 and P5PUP5 bits of P5PUP (x’00FFB5’) to enable pullup control of the SBO0 and STB0.
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Serial Interfaces Serial Interface Setup Examples Reception must be enabled for the circuit to detect a stop sequence. 2. When you perform step 1, the SBT0 output signal goes high. One cycle later, the SBO0 output signal also goes high, signalling the stop sequence. The SC0ISP flag of SC0STR becomes 1. The SC0IST and SC0ISP flags are both cleared by a write to or read from the serial port 0 transmit/receive buffer. Figure 5-13 shows an example timing chart.
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Serial Interfaces Serial Interface Setup Examples 5.6.5 Setting Up I 2 C Reception Using Serial Interface 0 This example illustrates the microcontroller as a master receiver in the I2C mode, using the SBO0 and SBT0 pins. When initiating master receiver mode, your program must always first transmit a byte of data. The master reception occurs during the interrupt service routine that runs after the data is transmitted. For an example setup of master transmission, see section 5.6.
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Serial Interfaces Serial Interface Control Registers 5.7 Serial Interface Control Registers Three registers control each of the serial interfaces: the serial port control register (SCnCTR), the serial transmit/receive buffer (SCnTRB), and the serial port status register (SCnSTR).
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Serial Interfaces Serial Interface Control Registers SCnICM: Serial port n I2C mode select 0: I2C mode off 1: I2C mode on SCnLN: Serial port n character length 0: 7-bit 1: 8-bit SCnPTY[2:0]: Serial port n parity bit select 000:None 001:Reserved 010:Reserved 011:Reserved 100:0 (output low) 101:1 (output high) 110:Even (1s are even) 111:Odd (1s are odd) SCnSB: Serial port n stop bit select (UART mode only) 0: 1-bit 1: 2-bit SCnS[1:0]: Serial port n clock source select The 00 and 10 settings are reserved
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Serial Interfaces Serial Interface Control Registers SC0STR/SC1STR: Serial Port n Status Register Bit: 7 6 5 4 3 2 1 0 SCn TBY SCn RBY SCn ISP SCn RXA SCn IST SCn FE SCn PE SCn OE Reset: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R x’00FD83’/x’00FD8B’ SCnSTR contains the error detection and status flags for the serial interfaces.
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Analog-to-Digital Converter Description 6 Analog-to-Digital Converter 6.1 Description The MN102H75K/85K contains an 8-bit charge redistribution A/D converter (ADC) that can process up to 12 channels. The reference clock is selectable to BOSC x 1/8 or 1/16. When BOSC is 24 MHz, you must set the reference clock to BOSC/8 (conversion rate = 4 µs) or higher.
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Analog-to-Digital Converter Block Diagram 6.3 ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 ADIN5 ADIN6 ADIN7 ADIN8 ADIN9 ADIN10 ADIN11 Block Diagram 128 64 32 16 8 4 2 1 1 M U X VDD VSS Storage of converted data Shift register for state information ANCTR ANNCH AN1CH AN11BUF-AN0BUF BOSC Divider Compare Interrupt generated INC Data registers 8-bit x 12 A/D interrupt request Figure 6-2 ADC Block Diagram 6.4 A/D Conversion Timing 6.4.
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Analog-to-Digital Converter A/D Conversion Timing 6.4.2 Single Channel/Single Conversion Timing When ANMD[1:0] = b’00’, the ADC converts one ADIN input signal a single time. An interrupt occurs when the conversion ends. Load the number of the channel to be converted to the AN1CH[3:0] field of the ADC control register (ANCTR). (The ANNCH[3:0] field is ignored in this mode.
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Analog-to-Digital Converter A/D Conversion Timing 6.4.4 Single Channel/Continuous Conversion Timing When ANMD[1:0] = b’10’, the ADC converts one ADIN input signal continuously. An interrupt occurs each time the conversion ends. Load the number of the channel to be converted in the AN1CH[3:0] field of the ADC control register (ANCTR). (The ANNCH[3:0] field is ignored in this mode.
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Analog-to-Digital Converter ADC Setup Examples 6.5 ADC Setup Examples 6.5.1 Setting Up Software-Controlled Single-Channel A/D Conversion This example illustrates single-channel conversion controlled by the software. The ADIN6 pin inputs an analog voltage signal (0.0 V–3.3 V) and the ADC converts it to 8-bit digital values. MN102H75K 3.3 V P11, ADIN6 0V Figure 6-8 Single-Channel A/D Conversion ■ To set up the input port: Set the P1MD2 bit of the port 1 output mode register (P1MD) to 1.
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Analog-to-Digital Converter ADC Setup Examples AN6BUF (example) Bit: 15 14 — 13 — 12 — — x’00FF14’ 11 10 — 9 — 8 — 7 6 5 4 3 2 1 0 ANn ANn ANn ANn ANn ANn ANn ANn BUF7 BUF6 BUF5 BUF4 BUF3 BUF2 BUF1 BUF0 — ANCTR set ANEN ADIN6 converting State Reference clock 1 2 3 4 10 11 12 VALID AN6BUF AN6BUF read Interrupt Figure 6-9 Timing of Software-Controlled Single-Channel A/D Conversion 6.5.
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Analog-to-Digital Converter ADC Setup Examples ■ To set up the input port: Set the P0DIR[5:3] bits of the port 0 I/O control register (P0DIR) to 0. This sets the ADIN2 (P05), ADIN1 (P04), and ADIN0 (P03) pins (P11) to general-purpose input. ■ To set up the ADC: Set the operating conditions in the ADC control register (ANCTR). Select multiple-channel, single-conversion mode (ANMD[1:0] = b’01’) and BOSC/8 as the clock source (ANCK[1:0] = b’10’). Set the conversion start/busy bit, ANEN, to 0.
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Analog-to-Digital Converter ADC Control Registers Timer 1 underflow Conversion Channel 0 Channel 1 Channel 2 Channel 0 Channel 1 Channel 2 Interrupts Figure 6-11 Timing of Hardware-Controlled Intermittent Three-Channel A/D Conversion 6.6 ADC Control Registers The ADC contains thirteen registers—one control register (ANCTR) and twelve data buffers (each associated with one of the ADIN pins).
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Analog-to-Digital Converter ADC Control Registers ANCTR: ADC Control Register Bit: 15 14 13 12 11 10 x’00FF00’ 9 8 AN AN AN AN AN AN AN AN NCH3 NCH2 NCH1 NCH0 1CH3 1CH2 1CH1 1CH0 7 6 AN EN AN TC 5 0 4 3 2 1 0 0 AN CK1 AN CK0 AN MD1 AN MD0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W ANNCH[3:0]: Channel select for multiple-channel conversion 0000: Convert ADIN0 0001: Convert ADIN0–ADIN1 001
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Analog-to-Digital Converter Cautions about Analog-to-Digital Converter 6.7 Cautions about Analog-to-Digital Converter The type of this Analog-to-Digital Converter is a sample-hold one, and so the current temporarily flows in conversion to charge the condenser of the samplehold circuit. For this reasons, the following settings are needed to get the accurancy of convension: 1. Impedance of analog input terminal must be below 8kΩ. 2.
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On-Screen Display Description 7 On-Screen Display 7.1 If you use the OSD function, the DMA function executes for both the text and graphics layers, even if your program does not use one of these layers. To prevent error, program data for the unused layer to meet the restrictions outlined here. The MN102H75K/85K contains an on-screen display (OSD) function composed of three layers: a text layer, a graphics layer, and a cursor layer.
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PLL Panasonic Semiconductor Development Company 154 Panasonic IRQ data addr SYSCLK R/W 48 MHz OSD GEXTE RAMEND (Reads text and graphics data) DMA block OSD registers indicates the control bit or field.
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On-Screen Display Power-Saving Considerations in the OSD Block 7.4 Power-Saving Considerations in the OSD Block Table 7-2 shows bits that can decrease the power consumption of the OSD block. This section explains how to use these bits. Table 7-2 Power-Saving Control Bits for the OSD OSDPOFF resets to 0. To operate the OSD, you must first set this bit to 1. ■ To turn off the OSD block to save power: 1. Write a 0 to OSD (OSD1, bit 10). 2. Wait for the next VSYNC input. 3.
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On-Screen Display OSD Operation 7.5 OSD Operation This section describes the basic operation of the OSD block. The remainder of section 7 provides more detailed specifications. 7.5.1 OSD Clock The OSD clock source is programmable to either the microcontroller system clock (OSC1, OSC2 pins) or a dedicated OSD clock (OSDXI, OSDXO pins). ■ See section 7.11, “Selecting the OSD Dot Clock,” on page 186, for information on setting the OSD clock frequency.
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On-Screen Display OSD Operation ■ Graphics layer The graphics layer contains tiled images. In the 16-color mode, each 4-bit dot on a tile can display one of 16 colors. Each tile can use either of two available color palettes, allowing a total of 32 colors in one display. The graphics layer also supports 2-, 4-, and 8-color modes. All the tiles in a single display screen must be in the same color mode. (For instance, an 8-color-mode tile cannot be displayed at the same time as a 16-color-mode tile.
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On-Screen Display OSD Operation 7.5.7 ■ Set CHP, CVP, GHP, and GVP for every line in the VRAM. If you do not, a software processing error may occur. ■ Conditions for VRAM Writes Text layer 1. The lead data for each line must be the color control code (COL) or the character code (CC). Never place the horizontal position (CHP), vertical position (CVP), or repeat (CCB) codes at the beginning of a line.
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On-Screen Display Standard and Extended Display Modes 7.6 Standard and Extended Display Modes Two modes are available for the graphics and cursor layers, standard and extended. In extended mode, the cursor layer can display four grouped graphic tiles rather than one. The graphics layer can display tiles that are two pixels taller than those used in standard mode, giving the graphic tiles the same dimensions as the characters in the text layer. 7.6.
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On-Screen Display Standard and Extended Display Modes Table 7-4 Associated Tiles for Cursor Tile Code Registers Graphic Tile Register Register Address (1) Upper left STC0 x’007F10’ (2) Upper right STC1 x’007F2A’ (3) Lower left STC2 x’007F2C’ (4) Lower right STC3 x’007F2E’ In standard mode, STC0 is the only cursor tile code register that is enabled.
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On-Screen Display Display Setup Examples 7.7 Display Setup Examples 7.7.1 Setting Up the Graphics Layer This section shows how to set up the graphics display data in the VRAM.
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On-Screen Display Display Setup Examples VP = x'3' HSZ= 1 (2x) HP = x'22' Line 1 VSZ = 3 (6x) GTC = x'000' Palette 1 GTC = x'055' Palette 2 Blank GTC = x'100' Palette 1 VP = x'40' Line 2 HSZ = 0 (1x) HP = x'4' VSZ = 0 (1x) 010 011 012 013 013 013 014 Blank 013 Palette 1 Palette 1 Palette 1 Palette 1 Palette 1 Palette 1 Palette 1 Palette 2 Blank Blank 016 Palette 2 Repeated tile VP = x'58' Line 3 HP = x'10' HSZ = 3 (4x) GTC = x'181' Palette 1 GTC = x'182' Palette 2 VSZ = 1 (2x) Display en
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On-Screen Display Display Setup Examples 7.7.2 Setting Up the Text Layer This section shows how to set up the text display data in the VRAM. ■ Register settings RAMEND (x’007F04’) = x’80FF’ (Text RAM end address: x’9FFF’) CIHP (x’007F1A’) = x’1020’ (CIHP = x’20’, CIHSZ = x’2’) CIVP (x’007F1C’) = x’1803’ (CIVP = x’03’, CIVSZ = x’3’) OSD3 (x’007F0A’) = x’0000’ (CAPM = x’0’) Table 7-6 Example Text VRAM Settings Line No. RAM Addr. RAM Data Data Type Description 1 9FFE 9FFC 9FFA 9FF8 9FF6 9FF4 ..
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On-Screen Display Display Setup Examples The text display starts one dot to the right of the HP setting. VP = x'3' HSZ = 2 (3x) HP = x'20' Line 1 VSZ = 3 (6x) CC = x'000' No shadow No outline Background col. = 2 Text color = 1 CC = x'001' No shadow Outline Background col. = 5 Text color = A CC = x'002' No shadow Outline Background col. = 5 Text color = A VP = x'40' Line 2 HSZ=0 (1x) CC=006 CC=007 CC=007 CC=007 CC=007 CC=007 CC=008 HP = x'4' VSZ = 1 (2x) Box shad.1 Char. shad Back col. 6 Text col.
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On-Screen Display VRAM 7.8 VRAM 7.8.
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On-Screen Display VRAM BLINK Specifies character blinking. 0: Disable 1: Enable BCOL[3:0] Specifies the background color (1 of 16 colors). CCOL[3:0] Specifies the foreground (character) color (1 of 16 colors). COL: Color Control Code (Closed-Caption Mode) ID Code: 10 CUNDL Specifies underlining. 0: Disable 1: Enable ITALIC Specifies italicization. 0: Disable 1: Enable FRAME Specifies character outlining (black). 0: Disable 1: Enable BLINK Specifies character blinking.
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On-Screen Display VRAM CHP: Character Horizontal Position Control Code ID Code: 11 CHSZ[1:0] Specifies the H size of the characters on the next line. 00: 1 dot = 1 VCLK period 01: 1 dot = 2 VCLK periods 10: 1 dot = 3 VCLK periods 11: 1 dot = 4 VCLK periods CSHT Specifies shutter operation for the next line. Setting this bit to 1 disables the shuttering function. You can disable and enable shuttering on a line-byline basis.
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On-Screen Display VRAM GCB[3:0] Specifies the number of times (up to 16) a blank or graphic tile is repeated. GPRT Specifies graphics color palette 1 or 2. 0: Palette 1 1: Palette 2 GTC[8:0] Specifies the address of one of 512 graphic tiles stored in the ROM. GHP: Graphics Horizontal Position Control Code ID Code: 11 GHSZ[1:0] Specifies the H size of the characters on the next line.
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On-Screen Display VRAM 7.8.2 VRAM Organization Graphics RAM Addresses (When GEXTE = 1) GRAMEND−40×N+5 Line N data GRAMEND−3F GRAMEND−3E GRAMEND−3D GRAMEND−3C GRAMEND−3B GRAMEND−3A GRAMEND−2F GRAMEND−2E GRAMEND−40×(N−1) x'008000' . . . Program Data and Stack Area GRAMEND−40×n+5 Line n data GRAMEND−40×(n−1) . . . Unused area Unused area Code 30 Code 29 . . .
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On-Screen Display VRAM GRAMEND−40×N+5 Line N data GRAMEND−3F GRAMEND−3E GRAMEND−3D GRAMEND−3C GRAMEND−3B GRAMEND−3A GRAMEND−2F GRAMEND−2E GRAMEND−40×(N−1) . . . GRAMEND−40×n+5 Line n data GRAMEND−40×(n−1) . . . Unused area Unused area Code 30 Code 29 . . .
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On-Screen Display VRAM 7.8.3 Cautions about the number of display code set to VRAM When the display lines are adjoined or overlapped, and the number of the above display code is extremely fewer than that of the below one, first line of the display line may not be output correctly. In OSD circuit, font data to display are read from ROM and stored to the buffer. The data in the buffer are overwritten, after the present display code is output, to the display data of the next line.
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On-Screen Display ROM 7.9 ROM 7.9.1 ROM Organization Text ROM Addresses Text character 16 bits Each character requires 36 bytes. Line 1 Line 2 Line 3 18 bits x’080000’ CROMEND−24×(M+1)+1 CROMEND−24×M Line 18 Code M text data Bit 15 . . . Program Data Area CROMEND−24×(m+1)+1 CROMEND−24×m Line 1 bits 7 to 0 CROMEND−22 Line 1 bits 15 to 8 CROMEND−21 Line 2 bits 7 to 0 CROMEND−20 Line 2 bits 15 to 8 CROMEND−1F Line 3 bits 7 to 0 . . .
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On-Screen Display ROM 7.9.2 Graphics ROM Organization in Different Color Modes The graphics layer supports up to sixteen colors, in the 16-color mode, but also supports 2-, 4-, and 8-color modes. The smaller the number of colors, the less ROM area required per tile. The figures in this section illustrate the ROM organization for each color mode. The example in figure 7-10 demonstrates the graphics ROM setup for line 16 of the code 00 data when the graphics layer is in 16-color mode.
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On-Screen Display ROM Graphic Tile Codes 2 colors ROMEND−80×N+1 N×4−1 4 colors N×2−1 8 colors 16 colors N × 4/3 − 1 N−1 . N is a multiple of 3. . . . . . . . . . . .
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On-Screen Display ROM Graphic Tile Codes 2 colors ROMEND−90×N+1 N×4−1 4 colors N×2−1 8 colors 16 colors N × 4/3 − 1 N−1 . N is a multiple of 3. . . . . . . . . . . . 03 04 06 ROMEND−1B0 ROMEND−18C ROMEND−168 ROMEND−144 ROMEND−120 ROMEND−FC ROMEND−D8 ROMEND−B4 ROMEND−90 ROMEND−6C ROMEND−48 ROMEND−24 ROMEND Required bytes per tile 0C 0B 05 0A 03 02 09 04 08 07 02 03 06 01 05 02 04 01 03 01 02 00 01 144 bytes 00 00 00 36 bytes 72 bytes 108 bytes 144 bytes See fig.7-19 See fig.
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On-Screen Display ROM ROMEND−7F ROMEND−78 ROMEND−77 128 bytes ROMEND−70 ROMEND−6F ROMEND−68 ROMEND−67 ROMEND−10 ROMEND−0F ROMEND−08 ROMEND−07 ROMEND 16 bits Line 1 data Graphics tile Line 2 data Line 1 Line 2 Line 3 Sheet 4 (16-color mode) Sheet 3 Line 3 data Sheet 2 ROMEND−7 Sheet 1 bits 7 to 0 Sheet 1 ROMEND−6 Sheet 1 bits 15 to 8 . . .
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On-Screen Display ROM ROMEND−8F ROMEND−88 ROMEND−87 144 bytes ROMEND−80 ROMEND−7F ROMEND−78 ROMEND−77 Line 1 data ROMEND−08 ROMEND−07 ROMEND Sheet 4 (16-color mode) Sheet 3 Line 3 data ROMEND−7 Sheet 1 bits 7 to 0 ROMEND−5 Sheet 3 bits 7 to 0 Line 18 1 dot = 4 bits = 16 colors ROMEND−2 Sheet 3 bits 15 to 8 Line 17 data ROMEND−1 Line 18 data Sheet 1 Sheet 2 bits 7 to 0 ROMEND−4 Sheet 2 bits 15 to 8 ROMEND−3 Line 1 Line 2 Line 3 Sheet 2 ROMEND−6 Sheet 1 bits 15 to 8 . . .
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On-Screen Display Setting Up the OSD 7.10 Setting Up the OSD 7.10.1 Setting Up the OSD Display Colors This section describes how to set up the display colors for the OSD. ■ To set up the color palettes: Write your settings to the color palette registers shown in table 7-8.
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On-Screen Display Setting Up the OSD ■ To set up the text display colors: Write to the fields described below. ♦ CCOL[3:0] (COL bits 3 to 0 in the RAM data) sets the color of the character. This value is in reference to the selected color palette (CPT0–CPTF). ♦ BCOL[3:0] (COL bits 7 to 4 in the RAM data) sets the background color. As with CCOL, this value is in reference to the selected color palette (CPT0–CPTF). ♦ FRAME (COL bit 9 in the RAM data) enables character outlining when set to 1.
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On-Screen Display Setting Up the OSD Translucency Selecting YS palette output, by setting the YSPLT bit of OSD1 (x’007F06’) to 1, disables the PRYM bit. With this setting, you must also set the TRPT and TRPTF bits to 1. You can specify transparency for individual color palettes if needed. The TRPTF bit allows you to make the color 15 translucent in all the palettes (CPTF, GPT1F, and GPT2F). RGB and YS are output at low levels for that color, and YM is output at the level specified for the palette.
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On-Screen Display Setting Up the OSD Table 7-9 RGB, YM, and YS Output Control Settings Waveform in figure 7-21 YSPLT PRYM TPRT TRPTF RGB YM YS 0 0 0 0 Color palettes 0 and F output low Color palettes 0 and F output low Color palettes 0 and F output low ➀ 0 0 0 1 Color palette 0 output low Color palette 0 output low Color palette 0 output low ➁ 0 0 1 0 Color palette F output low Color palette F output low Color palette F output low ➂ 0 0 1 1 — — — ➃ 0 1 0 0 Color
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On-Screen Display Setting Up the OSD Graphics layer Color palette 2 (YM3 = 0, YM2 = 0, YM1 = 0, YM0 = 0) Color palette 0 (YM3 = 0, YM2 = 0, YM1 = 0, YM0 = 1) Color palette 1 (YM3 = 1, YM2 = 0, YM1 = 0, YM0 = 1) RGB, YM, and YS signals are displayed at this line. TV Color palette F (YM3 = 1, YM2 = 0, YM1 = 0, YM0 = 1) Signal specified in color palette 0 is output.
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On-Screen Display Setting Up the OSD Color palette Bit 15 14 13 12 *** *** *** *** YM3 YM2 YM1 YM0 11 10 9 8 7 6 5 4 3 2 1 0 *** B3 *** B2 *** B1 *** B0 *** G3 *** G2 *** G1 *** G0 *** R3 *** R2 *** R1 *** R0 4 4 4 G B YM Digital input 4 R Internal DAC YM G B R Analog output RGBCNT (x'007F06', bit 1) Output YS to entire OSD display area (except transparent and semitransparent areas).
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On-Screen Display Setting Up the OSD 7.10.2 Text Layer Functions This section describes the character enhancement functions available in the text layer. ■ Outlining In both normal and closed-caption modes, writing a 1 to bit 9 (FRAME) of the COL setting in the VRAM causes an outline to appear around all characters following that COL. You can specify the color of the outline in the FRAME register (x’007FA2’). Figure 7-23 shows an example of character outlining.
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On-Screen Display Setting Up the OSD ■ Box shadowing In normal mode, writing a 1 to bit 12 (BSHAD1) of the COL setting in the VRAM causes a box shadow to appear around all characters following that COL. If COL bit 11 (BSHAD0) is 0, the color specified in the WBSHD register (x’007FA6’) appears on the top and left sides of the box and the color specified in the BBSHD register (x’007FA4’) appears on the bottom and right sides of the box. These positions are reversed if BSHAD0 is 1.
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On-Screen Display Setting Up the OSD ■ Italicizing In closed-caption mode, writing a 1 to bit 10 (ITALIC) of the COL setting in the VRAM italicizes all characters following that COL. Figure 7-26 shows an example of an italicized character. ■ Underlining 18 dots In closed-caption mode, writing a 1 to bit 11 (CUNDL) of the COL setting in the VRAM underlines all characters following that COL. Figure 7-26 shows an example of an underlined character.
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On-Screen Display Setting Up the OSD 7.10.3 Display Sizes ■ Graphic tile sizes ×1 b'00' ×2 b'01' 16 ×3 b'10' ×4 b'11' 32 48 GHSZ[1:0] 64 b'00' ×1 16 b'01' ×2 32 b'10' ×4 64 b'11' ×6 96 GVSZ[1:0] The settings shown are for interlaced displays. In progressive displays, the vertical size settings (GVSZ[1:0]) are as follows: 01 = 1x, 10 = 2x, and 11 = 3x. The 00 setting is reserved.
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On-Screen Display Setting Up the OSD ■ Character sizes ×1 b'00' ×2 b'01' 16 ×3 b'10' ×4 b'11' 32 48 CHSZ[1:0] 64 b'00' ×1 18 b'01' ×2 36 b'10' ×4 72 b'11' ×6 108 CVSZ[1:0] The settings shown are for interlaced displays. In progressive displays, the vertical size settings (CVSZ[1:0]) are as follows: 01 = 1x, 10 = 2x, and 11 = 3x. The 00 setting is reserved. In addition, in closed-caption mode, only the b’00’, b’01’, and b’11’ settings are available for CVSZ[1:0].
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On-Screen Display Setting Up the OSD 7.10.4 Setting Up the OSD Display Position This section describes how to control the positioning of the OSD. ■ To set up the horizontal position: Cursor ♦ Write the horizontal position of the cursor to the SHP[9:0] field (x’007F12’). ♦ Valid range: SHP ≥ x’0C’ Graphics ♦ Write the horizontal position of the first line in the display to the GIHP[9:0] field (x’007F16’).
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On-Screen Display Setting Up the OSD ■ To set up the vertical position: Cursor ♦ Write the vertical position of the cursor to the SVP[9:0] field (x’007F14’). ♦ Valid range: x’3F0’ − (no. of H scan lines) ≥ SHP ≥ x’03’ Graphics When you write new values to the GIVP and CIVP fields, the settings take effect on the next VSYNC pulse. This means that changes are reflected in the next display screen rather than the current one.
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On-Screen Display DMA and Interrupt Timing 7.11 DMA and Interrupt Timing This section describes how the MN102H75K/85K handles the timing of direct memory access (DMA) transfers of OSD data and OSD interrupts. ■ DMA On both the text and graphics layers, the microcontroller reads the line 1 data from the RAM as it scans line 1 onto the display. For line 2 and following lines, it reads the data as it scans the display start for the preceding line.
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On-Screen Display DMA and Interrupt Timing 12Ts Scan line 1 4nTs 5Ts Text DMA Television Screen 4nTs Graphics DMA Text interrupt Graphics interrupt Graphics interrupt Line G1 Line C1 Graphics DMA Graphic display Text DMA Text display Text interrupt Text display Graphic display Text display Line C2 Text display Line G2 Graphic display Horizontal sync pulse Figure 7-30 DMA and Interrupt Timing for the OSD Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Man
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On-Screen Display Selecting the OSD Dot Clock 7.12 Selecting the OSD Dot Clock This section describes how to set up the OSD dot clock. ■ Selecting the clock source The source for the OSD dot clock is programmable to either the 4-MHz clock supplied through the OSC1 and OSC2 pins, then multiplied by the PLL circuit to 48 MHz, or a dedicated clock supplied through the OSDXI and OSDXO pins.
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On-Screen Display Controlling the Shuttering Effect 7.13 Controlling the Shuttering Effect The MN102H75K/85K OSD achieves a shuttering effect using four programmable shutters—two vertical and two horizontal. With this feature, you can shutter any portion of the OSD display, or you can combine shuttering with a wipe-out effect to create a smooth appearing and disappearing effect. To prevent flickering and shadows on the display, only write to the registers during the VSYNC cycle. 7.13.
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On-Screen Display Controlling the Shuttering Effect HSHT0 HSHT1 VSHT0 VSON0 = VSON1 = 1: V shutters 0 and 1 on HSON0 = HSON1 = 1: H shutters 0 and 1 on VSP0 = 0: V shutter 0 shutters below VSP1 = 1: V shutter 1 shutters above HSP0 = 0: H shutter 0 shutters to the right HSP1 = 1: H shutter 1 shutters to the left SHTRAD = 0: All shutters ANDed VSHT1 Television screen HSHT0 Shuttered region HSHT1 VSHT0 VSON0 = VSON1 = 1: V shutters 0 and 1 on HSON0 = HSON1 = 1: H shutters 0 and 1 on VSP0 = 0: V shut
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On-Screen Display Controlling the Shuttering Effect 7.13.2 Controlling Shutter Movement Enabling the shutter movement function in the registers allows the shuttered area to expand or contract over time, producing a wipe-in or wipe-out effect. This allows the OSD display to appear or disappear without an abrupt transition. Table 7-13 shows the register settings required for this function, and figure 7-32 shows four setup examples.
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On-Screen Display Controlling the Shuttering Effect HSHT0 HSHT1 VSHT0 VSON0 = VSON1 = 1: V shutters 0 and 1 on HSON0 = HSON1 = 1: H shutters 0 and 1 on VSP0 = 1: V shutter 0 shutters above VSP1 = 0: V shutter 1 shutters below HSP0 = 1: H shutter 0 shutters to the left HSP1 = 0: H shutter 1 shutters to the right SHTRAD = 1: All shutters ORed VSHT1 Television screen Shuttered region This example shows V shutter 0 moving downward. It shutters both the text and the background color in the text layer.
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On-Screen Display Controlling the Shuttering Effect 7.13.3 Controlling Shuttering Effects Through register settings, you can independently control shuttering for text, text background, graphics, and color background. You can also output blanks to the shuttered area. You cannot shutter the cursor layer. Table 7-13 shows the register settings required for these effects.
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On-Screen Display Controlling the Shuttering Effect HSHT0 HSHT1 VSHT0 CCSHT = 0: Shuttering of text foreground disabled BCSHT = 0: Shuttering of text background disabled ABCDE VSHT1 Television screen HSHT0 Shuttered region HSHT1 VSHT0 CCSHT = 1: Shuttering of text foreground enabled BCSHT = 0: Shuttering of text background disabled CDE VSHT1 Television screen HSHT0 HSHT1 VSHT0 CCSHT = 0: Shuttering of text foreground disabled BCSHT = 1: Shuttering of text background enabled ABCDE VSHT1 Th
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On-Screen Display Controlling the Shuttering Effect HSHT0 HSHT1 VSHT0 CCSHT = 0: Shuttering of text disabled BCSHT = 0: Shuttering of text background disabled SHTBLK = 1: Shuttered area is blank ABCDE VSHT1 Shuttered area Shuttered area is blank (black).
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On-Screen Display Field Detection Circuit 7.14 Field Detection Circuit 7.14.1 Block Diagram HSYNC System clock R Divide by 3 Database Upper 4 bits 4 7-bit counter x’007F0E’ EVOD (FREG[13:10]) VSYNC leading edge detection T-FF LOADN1 4 D-FF x 4 (N1) x’007F0E’ EVOD (FREG[23:20]) LOADN2 4 D-FF x 4 (N2) 4 4 N1CNT N2CNT Vertical display controller EOMON Comparator EOSEL FRMON Figure 7-36 Field Detection Circuit Block Diagram 7.14.
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On-Screen Display Field Detection Circuit Table 7-15 EOMON Output Criteria EOMON Output FRMON N1, N2 Relationship 0 Load to N2 next EOSEL = 0 EOSEL = 1 N1 > N2 0 1 N1 < N2 1 0 N1 = N2 1 Load to N1 next Complement previous Complement previous N1 > N2 1 0 N1 < N2 0 1 N1 = N2 Complement previous Complement previous 7.14.
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On-Screen Display OSD Registers 7.15 OSD Registers All registers in OSD block cannot be written by byte (by word only). Read by byte is possible.
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On-Screen Display OSD Registers is x’900F’ to x’9FFF’, with a programmable range from x’00’ to x’FF’.
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On-Screen Display OSD Registers STC3: Cursor Tile Code Register 3 Bit: 15 14 13 12 11 10 — — — — — — x’007E2E’ 9 8 7 6 5 4 3 2 1 0 SPRT3 STC38 STC37 STC36 STC35 STC34 STC33 STC32 STC30 STC30 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SPRT3: Cursor 3 color palette select 0: Graphics color palette 1 1: Graphics color palette 2 STC3[8:0]: Cursor 3 Tile Code Use the same ROM data as that used for t
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On-Screen Display OSD Registers 00: 1 dot = 1 VCLK period 01: 1 dot = 2 VCLK periods 10: 1 dot = 3 VCLK periods 11: 1 dot = 4 VCLK periods GISHT: Graphics initial shutter control 0: Shutter control on 1: Shutter control off GIHP[9:0]: Graphics initial horizontal position GIVP: Graphics Initial Vertical Position Register Bit: 15 — 14 — 13 12 11 10 — GI VSZ1 GI VSZ0 — 9 8 7 x’007F18’ 6 5 4 3 2 1 0 GIVP9 GIVP8 GIVP7 GIVP6 GIVP5 GIVP4 GIVP3 GIVP2 GIVP1 GIVP0 Reset: 0 0 0 0 0 0 0
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On-Screen Display OSD Registers CIVSZ[1:0]: Text initial vertical size Table 7-18 Text Vertical Size Settings 1 Dot Size CIVSZ[1:0] Setting Interlaced Displays Progressive Displays 00 01 10 11 1 H scan line 2 H scan lines 4 H scan lines 6 H scan lines Reserved 1 H scan line 2 H scan lines 3 H scan lines CIVP[9:0]: Text initial vertical position EVOD: Display Start Field Control Register Bit: 15 14 13 12 11 10 9 — — — — — EO SEL FR MON 8 7 x’007F0E’ 6 5 4 3 2 1 0 EO FREG FREG FREG
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On-Screen Display OSD Registers OSD1: OSD Register 1 Bit: 15 — 14 — 13 — 12 — x’007F06’ 11 — 10 9 8 OSD OSC SEL1 OSC SEL0 7 XIO 6 5 HPOL VPOL 4 3 2 YS POL YS PLT — 1 0 YCNT RGBC Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 0: Off 1: On OSCSEL[1:0]: Oscillator select A write to the OSD bit of OSD1 takes effect on the next leading edge of VSYNC.
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On-Screen Display OSD Registers OSD2: OSD Register 2 Bit: 15 14 13 12 x’007F08’ 11 10 9 8 7 6 5 4 3 2 1 0 SPEX GCOL GCOL VCLK VCLK VCLK GTHT GEXTE PRYM TRPTF TRPT COLB CGPR SOUT GOUT COUT T 1 0 2 1 0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SPEXT: Cursor extended mode select 0: Standard mode (16 x 16 pixels) 1: Extended mode (32 x 32 pixels) GTHT: Graphic tile height select 0: 16 pixels
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On-Screen Display OSD Registers OSD3: OSD Register 3 Bit: 15 — 14 — 13 — 12 — x’007F0A’ 11 10 — 9 — 8 — — 7 — 6 — 5 4 3 2 1 0 BLIN CANH EONL BFLD UNDF CAPM K Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R/W R/W R/W R/W R/W R/W BLINK: Character blinking control Controls blinking for text-layer characters with BLINK set in the COL code.
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On-Screen Display OSD Registers VSHT1: Vertical Shutter 1 Register Bit: 15 — 14 — 13 12 11 10 x’007F22’ 9 VSON VSMP VST1 VSP1 VSM1 1 1 9 8 7 6 5 4 3 2 1 0 VST1 VST1 VST1 VST1 VST1 VST1 VST1 VST1 VST1 8 7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 6 5 4 3 2 VSON1: Vertical shutter 1 on/off 0: Off 1: On VSP1: Vertical shutter 1 shuttering direction 0: Shutter below 1: Shutte
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On-Screen Display OSD Registers HSHT1: Horizontal Shutter 1 Register Bit: 15 — 14 — 13 12 11 10 9 HSON HSMP HST1 HSP1 HSM1 1 1 9 8 x’007F26’ 7 6 5 4 3 2 1 0 HST1 HST1 HST1 HST1 HST1 HST1 HST1 HST1 HST1 8 7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 1 0 GSHT BC SHT CC SHT HSON: Horizontal shutter 1 on/off 0: Off 1: On HSP1: Horizontal shutter 1 shuttering direction 0: Shu
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On-Screen Display OSD Registers CPT0–CPTF: Text Palette Colors 0–15 Registers Bit: x’007F80’–x’007F9E’ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPTn YM3 CPTn YM2 CPTn YM1 CPTn YM0 CPTn B3 CPTn B2 CPTn B1 CPTn B0 CPTn G3 CPTn G2 CPTn G1 CPTn G0 CPTn R3 CPTn R2 CPTn R1 CPTn R0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: W W W W W W W W W W W W W W W W These registers contain the colors used in the text layer.
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On-Screen Display OSD Registers BBSHD: Black Box Shadowing Register Bit: 15 BB SHD YM3 14 BB SHD YM2 13 BB SHD YM1 12 BB SHD YM0 11 BB SHD B3 10 BB SHD B2 9 BB SHD B1 8 BB SHD B0 x’007FA4’ 7 BB SHD G3 6 BB SHD G2 5 BB SHD G1 4 BB SHD G0 3 BB SHD R3 2 BB SHD R2 1 BB SHD R1 0 BB SHD R0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: W W W W W W W W W W W W W W W W This register contains the color used as black in box shadowing.
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On-Screen Display OSD Registers GPT20–GPT2F: Graphics Palette 2 Colors 0–15 Registers x’007FE0’–x’007FFE’ Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n YM3 YM2 YM1 YM0 B3 B2 B1 B0 G3 G2 G1 G0 R3 R2 R1 R0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: W W W W W W W W W W W W W W W W These registers contain one of two sets of colors used in the graphics layer.
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IR Remote Signal Receiver Description 8 IR Remote Signal Receiver 8.1 fSYSCLK = 12 MHz in all of the examples and descriptions in this section. In addition, fPWM1 = fSYSCLK/23, fPWM3 = fSYSCLK/25, fPWM5 = fSYSCLK/27, fPWM6 = fSYSCLK/28, and fPWM8 = fSYSCLK/210. Description The MN102H75K/85K contains a remote signal receiver that processes signals in two formats: Household Electrical Appliance Manufacturers Association (HEAMA) format and 5-/6-bit format.
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4 RMLD: x’007EAC’ 2 6 Noise filter MN102H75K/F75K/85K/F85K LSI User Manual 217 Panasonic RMIR: x’007EA2’ 7 6 5 4 3 2 1 0 x’00’ (2 LSBs) CK Sampling 12 MHz, 0.
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IR Remote Signal Receiver IR Remote Signal Receiver Operation 8.3 IR Remote Signal Receiver Operation 8.3.1 Operating Modes The IR remote signal receiver has three operating modes: HEAMA, 5-/6-bit, and HEAMA–5-/6-bit automatic detect. Set the mode in the MODAUTO and MODSEL bits of the interrupt control register, RMIR. The FMTMON bit of the interrupt status register, RMIS, monitors the operating mode. In automatic detect mode, the microcontroller checks the interval between remote signal edges.
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IR Remote Signal Receiver IR Remote Signal Receiver Operation 8.3.3 8-Bit Data Reception Resetting the 8-bit data reception counter allows the microcontroller to receive 8bit data, either with or without a leader. The software can reset the counter using the BCRSTE and BCEDGS bits of the interrupt status register, RMIS. The counter can also be reset by an external reset or a hardware reset at leader detection. Set BCRSTE to enable resets to the 8-bit data reception counter.
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IR Remote Signal Receiver IR Remote Signal Receiver Operation 8.3.4 Identifying the Data Format The microcontroller determines the logic levels of the data by testing the interval between remote signal edges. Table 8-1 shows the intervals that the microcontroller interprets as 0 and 1 for both HEAMA and 5-/6-bit formats. Table 8-2 shows the conditions for identifying long and short data.
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IR Remote Signal Receiver IR Remote Signal Receiver Operation 8.3.5 Generating Interrupts The IR remote signal receiver has four interrupt vectors: leader detection, trailer detection, 8-bit data reception detection, and pin edge detection. This section describes the operation for each of them. 8.3.5.1 Leader Detection An interrupt occurs when the circuit detects a data leader. It detects leaders by testing the interval between remote signal edges. Table 8-3 shows the conditions.
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IR Remote Signal Receiver IR Remote Signal Receiver Operation 8.3.6 Use bit 7 (SP) in the RMLD register to toggle the noise filter sampling frequency between PWM6/PWM8 and PWM3/ PWM5. Controlling the SLOW Mode The MN102H series microcontrollers have two operating modes: NORMAL and SLOW. (See section 3.1, “CPU Modes,” on page 72.) In SLOW mode, fSYSCLK = 2 MHz, which affects the frequencies of the PWM3 clock and noise filter sampling (PWM6/PWM8).
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IR Remote Signal Receiver IR Remote Signal Receiver Control Registers 8.4 IR Remote Signal Receiver Control Registers All registers in RMC block cannot be written by byte (by word only). Read by byte is possible.
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IR Remote Signal Receiver IR Remote Signal Receiver Control Registers All registers in RMC block cannot be written by byte (by word only). Read by byte is possible. RMIR: Remote Signal Interrupt Control Register Bit: 7 6 5 4 MOD AUTO MOD SEL FILTR E POL SEL 3 2 LEADER TRAILR E E 1 0 DAT8 E EDME E Reset: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W x’007EA2’ RMIR controls the operating modes and interrupt operations for the receiver circuit.
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IR Remote Signal Receiver IR Remote Signal Receiver Control Registers RMIS: Remote Signal Interrupt Status Register Bit: 7 6 5 4 BC RSTE BC EDGS FMT MON 3 2 DOMES M56BIT TRAILR D D D 1 0 DAT8 D EDGE D Reset: 0 0 0 0 0 0 0 0 R/W: R/W R/W R R/W R/W R/W R/W R/W x’007EA0’ RMIR indicates the detection and operation status of remote signal interrupts. It is a 16-bit access register.
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IR Remote Signal Receiver IR Remote Signal Receiver Control Registers RMLD: Remote Signal Leader Value Set Register Bit: 7 6 5 4 3 2 1 0 SP SPSLW — — LD3 LD2 LD1 LD0 Reset: 0 0 0 0 0 1 1 0 R/W: R/W R/W R R R/W R/W R/W R/W x’007EAC’ RMLD is a 16-bit access register.
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Closed-Caption Decoder Description 9 Closed-Caption Decoder 9.1 Description The MN102H75K/85K contains two identical closed-caption decoder circuits, CCD0 and CCD1. The decoders extract encoded captions from composite video signals. Figure 9-1 provides a block diagram of the decoders, and section 9.3, “Functional Description,” on page 228, describes the circuit’s main blocks: the analog-to-digital converter, clamping circuit, sync separator circuit, data slicer, controller, and sampling circuit.
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Closed-Caption Decoder Functional Description The constants shown in figures 9-2 to 9-4 are recommended values only. Operation at these values is not guaranteed. 9.3 Functional Description 9.3.1 Analog-to-Digital Converter The analog-to-digital converter (ADC) converts the clamped video signal to 8-bit digital data using a 12-MHz sampling clock. Figure 9-2 shows an example configuration using the recommended external pin connections. In this example, both caption decoders are used.
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Closed-Caption Decoder Functional Description Table 9-2 Caption decoder register setting VBI control ADC control Use two caption decoders caption 0 ON(PCNT0.bp0=0) ON(PCNT0.bp4=1) caption 1 ON(PCNT0.bp1=0) ON(PCNT0.bp5=1) Use one caption decoder caption 0 ON(PCNT0.bp0=0) ON(PCNT0.bp4=1) no caption 1 OFF(PCNT0.bp1=1) OFF(PCNT0.bp5=0) No use caption decoder no caption 0 OFF(PCNT0.bp0=1) OFF(PCNT0.bp4=0) no caption 1 OFF(PCNT0.bp1=1) OFF(PCNT0.bp5=0) 9.3.2 Clamp control (P3MD.
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Closed-Caption Decoder Functional Description Table 9-4 Current Level Control Current Source Low Current Control Conditions Medium Current High Current (1) (2) (3) (4) (5) (6) 10 ≤ A Off On Off On Off On 4≤A≤9 Off On Off On Off Off 1≤A≤3 Off On Off Off Off Off A= 0 Off Off Off Off Off Off -3 ≤ A ≤ -1 On Off Off Off Off Off -9 ≤ A ≤ -4 On Off On Off Off Off A ≤ -10 On Off On Off On Off Notes: 1. A = compare level - reference level 2.
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ADDATA[7:0] MN102H75K/F75K/85K/F85K LSI User Manual 231 Panasonic BPPST[8:0] Backporch gate level generator SCMING[9:0] Minimum sync tip load pulse generator HP BPPG MINP LPFOUT[6:0] LPF1OUT[6:0] BPGATE NFSW[1:0] LPF BPLV[6:0] SYNCMIN[6:0] PCLV[6:0] VBION SAFE CLMODE[1:0] Clamping controller CVBSSEL COMPSY HSEPSAMP VSEPSAMP Clamp control pulse signal CLM BSP[5:0] PSP[5:0] Composite sync separator Figure 9-6 Sync Separator Circuit Block Diagram BPLV[6:0] Pedestal level detec
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Closed-Caption Decoder Functional Description Table 9-6 Control Registers for Sync Separator Circuit Register Page CCDO Address CCD1 Address Description Register for setting the sync separator level SPLV 244 x’007ECA’ x’007EEA’ Sync separator level set register Register for controlling the sync separator clock FQSEL 243 x’007EC2’ x’007EE2’ Frequency select register Registers for controlling the HSYNC separator HSEP1 246 x’007ECE’ x’007EEE’ HSYNC separator control register 1 HSEP2 246 x
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Closed-Caption Decoder Functional Description 9.3.3.2 VSYNC Separator The VSYNC separator extracts the VSYNC signal from the composite signal. Like the HSYNC separator, it contains programmable methods for eliminating noise. The VCNT register contains these settings. Masking the 0H to 127H range (by setting the VSEPSEL bit of VCNT to 0) prevents VSYNC errors due to noise. See figure 9-8. VSYNC 127H Masked signal Figure 9-8 VSYNC Masking 9.3.3.
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Closed-Caption Decoder Functional Description Table 9-7 provides the registers used to control and monitor the data slicer. See the page number indicated for register and bit descriptions.
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Closed-Caption Decoder Functional Description 9.3.5.1 CRI Detection for Sampling Clock Generation The decoder captures the caption data on the rising edge of the CRI pulse. To achieve this, it contains a circuit to accurately detect the CRI pulse rises and to generate a data sampling clock. CRI Data 21 HSYNC CRI2S CRI2E CRI detection This interval determines the sampling clock timing. Figure 9-10 Sampling Clock Timing Determination 9.3.5.
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Closed-Caption Decoder Closed-Caption Decoder Registers 9.4 Closed-Caption Decoder Registers All registers in Closed-caption Decoder block cannot be written by byte (by word only). Read by byte is possible.
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Closed-Caption Decoder Closed-Caption Decoder Registers FCCNT: VBI Decoding Format Select Register (FCCNTW Bit: For designs using the closed-caption decoder, always tie the FCCNT register to x’0008’.
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Closed-Caption Decoder Closed-Caption Decoder Registers MAXMIN: CRI Interval Maximum and Minimum Register (MAXMINW Bit: 15 14 13 12 11 10 9 8 7 6 5 x’007E02’ x’007E22’) 4 3 2 1 0 MAX7 MAX6 MAX5 MAX4 MAX3 MAX2 MAX1 MAX0 MIN7 MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R/W: R R R R R R R R R R R R R R R R MAX[7:0]: Maximum value during the CRI interval Valid range: x’00’ to x’FF’ MIN[7:0]: Minimum value during the CRI interval
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Closed-Caption Decoder Closed-Caption Decoder Registers HNUM: HSYNC Count Register (HNUMW Bit: 15 — 14 — 13 — 12 VBIIRQ 4 11 VBIIRQ 3 10 VBIIRQ 2 x’007E06’ x’007E26’) 9 VBIIRQ 1 8 VBIIRQ 0 7 6 SB FLAG — 5 4 3 2 1 0 — HNU M4 HNU M3 HNU M2 HNU M1 HNU M0 Reset: 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W R R R R R R R R This register allows you to time the interrupt occurring after the line 21 data capture to a line other than line
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Closed-Caption Decoder Closed-Caption Decoder Registers CRIFA: CRI Frequency Width Register A (CRIFAW Bit: 15 14 13 12 11 10 9 8 x’007E0C’ x’007E2C’) 7 6 5 4 3 2 1 0 CRI2 CRI2 CRI2 CRI2 CRI2 CRI2 CRI2 CRI2 CRI1 CRI1 CRI1 CRI1 CRI1 CRI1 CRI1 CRI1 FQW7 FQW6 FQW5 FQW4 FQW3 FQW2 FQW1 FQW0 FQW7 FQW6 FQW5 FQW4 FQW3 FQW2 FQW1 FQW0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R The CRIFA and CRIFB registers store the CRI cycles from ri
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Closed-Caption Decoder Closed-Caption Decoder Registers CRI1E: CRI Capture Stop Timing Control Register 1 (CRI1EW Bit: 15 — 14 — 13 — 12 — 11 — 10 9 8 7 6 x’007E12’ x’007E32’) 5 4 3 2 1 0 CRI1E CRI1E CRI1E CRI1E CRI1E CRI1E CRI1E CRI1E CRI1E CRI1E CRI1E 10 9 8 7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CRI1E[10:0]: Stop position for CRI capture 1 Valid range: x’000’ to x’7FF’ CRI2S: C
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Closed-Caption Decoder Closed-Caption Decoder Registers DATAE: Data Capture Stop Timing Control Register (DATAEW Bit: 15 14 13 12 11 — — — — — x’007E1A’ x’007E3A’) 10 9 8 7 6 5 4 3 2 1 0 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA E E E E E E E E E E E 10 9 8 7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DATAE[10:0]: Stop position for data capture Set this value high enough to allo
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Closed-Caption Decoder Closed-Caption Decoder Registers FQSEL: Frequency Select Register (FQSELW Bit: 15 — x’007EC2’ x’007EE2’) 14 13 12 11 10 9 8 — VFQ DIV5 VFQ DIV4 VFQ DIV3 VFQ DIV2 VFQ DIV1 VFQ DIV0 7 — 6 — 5 — 4 3 2 1 0 — FQ DIV3 FQ DIV2 FQ DIV1 FQ DIV0 Reset: 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 R/W: R R R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W In this register, set the sampling cycle for separating the HSYNC and VSYNC signals from the
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Closed-Caption Decoder Closed-Caption Decoder Registers Use this register to specify the position for capturing the pedestal level value used during pedestal clamping. Specify a number of ADC clocks after the leading edge of HSYNC. The valid range is x’000’ to x’1FF’, and the recommended setting is x’003C’.
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Closed-Caption Decoder Closed-Caption Decoder Registers Composite signal from ADC Compare Composite sync PSP MUX BSP CLMODE Figure 9-15 BSP and PSP Multiplexing BSP[5:0]: Sync separator level for pedestal clamping Sync separator level = (sync tip level/2) + BSP[5:0]. The valid range is x’00’ to x’3F’.
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Closed-Caption Decoder Closed-Caption Decoder Registers HSEP1: HSYNC Separator Control Register 1 (HSEP1W Bit: 15 14 13 12 11 — — — — — x’007ECE’ x’007EEE’) 10 9 8 7 6 5 4 3 2 1 0 HS HS HS HS HS HS HS HS HS HS HS FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ 10 9 8 7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W HSFREQ[10:0]: Correction HSYNC frequency Set the correction HSYNC cycle in
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Closed-Caption Decoder Closed-Caption Decoder Registers HDISTW: Sync Separator Detection Control Register 2 HDISTWW Bit: 15 — 14 13 — 12 — — 11 10 — 9 — 8 7 6 5 x’007ED6’ x’007EF6’) 4 3 2 1 0 HDIST HDIST HDIST HDIST HDIST HDIST HDIST HDIST HDIST W8 W7 W6 W5 W4 W3 W2 W1 W0 — Reset: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W HDISTW[8:0]: HSYNC count setting the interval for sync separation detection In this
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Closed-Caption Decoder Closed-Caption Decoder Registers CLPCND1: Clamping Control Signal Status Register 1 (CLPCNDW Bit: 15 — 14 — 13 — 12 11 — — 10 — 9 — 8 — 7 6 5 x’007EDC’ x’007EFC’) 4 3 2 1 0 SAFE XPED XPE PED PE SAFEP CLPP CLPN N UP DOWN UP DOWN Reset: 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 R/W: R R R R R R R R R R R R R R R R This register is for monitoring the status of the clamping current source switch shown in figure 9-5 on page 229.
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Pulse Width Modulator Description 10 Pulse Width Modulator 10.1 Description For information on the SLOW mode, see section 3.1, “CPU Modes.” The MN102H75K/85K contains seven 8-bit pulse width modulators (PWMs) with a minimum pulse width of 16/fSYSCLK and an output waveform cycle of 212/fSYSCLK. (With a 4-MHz oscillator, 16/fSYSCLK = 1.33 µs (8 µs for SLOW mode) and 212/fSYSCLK = 341.3 µs (2 ms for SLOW mode).) The PWM ports are 3.3-volt, open-drain outputs.
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Pulse Width Modulator Block Diagram 10.2 Block Diagram Data bus 8 PWM0 - PWM6 MSB 7 x'007E70' - x'007E7C' 6 5 4 3 2 1 0 PnPUP PnCNT fPWM PWMn DAC output I/O control PWM (8-bit) MUX (P15 - P17, P20 - P23) PnDIR Port Note: With a 4-MHz oscillator: fPWM = fSYSCLK/16 Output pulse cycle = 28/fPWM = 341.3 µs Minimum pulse width = 1/fPWM = 1.33 µs tLOW = (PWMn + 1) × 0.
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I/O Ports Description 11 I/O Por ts 11.1 Description The MN102H75K/85K contains 50 pins that form general-purpose I/O ports. Ports 0, 1, 2, 3, 4, and 5 are 8-bit ports, and port 6 is a 2-bit port. All of these pins have alternate functions. (Ports 7 and 8 are only available with the quad flat package.
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I/O Ports I/O Port Circuit Diagrams 11.
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P0PUPn 0: P03, P04, P05, P06, P07, 1: ADIN0, ADIN1, ADIN2, ADIN3, ADIN4 P0MDn 0: Port input 1: Port output P0DIRn 0: Port low output 1: Port high output Pin P0OUTn P0INn ADIN0, ADIN1, ADIN2, ADIN3, ADIN4 Figure 11-2 P03/ADIN0 to P07/ADIN4 (Port 0) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 253 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P1PUPn 0: P10/IRQ1, P11/IRQ2, P12/IRQ3 1: ADIN5, ADIN6, ADIN7 P1MD(2n) 0: Port input 1: Port output P1DIRn 0: Port low output 1: Port high output Pin P1OUTn P1INn Schmidt trigger IRQ1, IRQ2, IRQ3 ADIN5, ADIN6, ADIN7 Figure 11-3 P10/ADIN5/IRQ1, P11/ADIN6/IRQ2, and P12/ADIN7/IRQ3 (Port 1) Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual 254 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P1PUPn 00: P13, P14 01: WDOUT, STOP 10: ADIN8, ADIN9 P1MD(2n) P1MD(2n+1) 0: Port input 1: Port output P1DIRn 0: Port low output 1: Port high output P1OUTn Pin WDOUT, STOP P1INn ADIN8, ADIN9 Figure 11-4 P13/ADIN8/WDOUT and P14/ADIN9/STOP (Port 1) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 255 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P1PUPn 00: P15,P16 01: PWM0,PWM1 10: ADIN10,ADIN11 P1MD(2n) P1MD(2n+1) 0: Port input 1: Port output P1DIRn PWM0,PWM1 0: Port low output 1: Port high output Pin P1OUTn P1INn ADIN10,ADIN11 Figure 11-5 P15/ADIN10/PWM0 and P16/ADIN11/PWM1 (Port 1) Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual 256 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P1PUPn P2PUPn 0: P17, P20, P21, P22, P23 1: PWM2, PWM3, PWM4, PWM5, PWM6 0: Port input 1: Port output P1MD(2n) P2MD(2n) 0 P1DIRn P2DIRn M U PWM2, PWM3, PWM4, PWM5, PWM6 0: Port low output 1: Port high output 1 P1OUTn P2OUTn X 0 M Pin U 1 Low output X P1INn, P2INn Figure 11-6 /PWM2 (Port 1), P20/PWM3, P21/PWM4, P22/PWM5, and P23/PWM6 (Port 2) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P2PUP4 00: P24 01: SBT1 10: TM4IC P2MD8 P2MD9 0: Port input 1: Port output P2DIR4 0: Port low output 1: Port high output Pin P2OUT4 SBT1 output 0: Push/pull 1: Open-drain (I2C mode) ODASCI1 P2IN4 Schmidt trigger TM4IC input SBT1 input Figure 11-7 P24/TM4IC/SBT1 (Port 2) To use as SBT1,set P2MD8 and P2MD9 to 0.
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P2PUP7 0: P27 1: TM0IO P2MD14 0: Port input 1: Port output P2DIR7 0: Port low output 1: Port high output 0 P2OUT7 M Pin U 1 TM0IO output X P2IN7 TM0IO input Figure 11-8 P27/TM0IO (Port 2) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 259 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P3PUPn P4PUPn 0: DAC output 1: Digital output (OSD1)bp0 0: P35, P36, P37, P40 1: DAROUT/R, DAGOUT/G DABOUT/B, DAYMOUT/YM 0: Port input 1: Port output 0: Port low output 1: Port high output P3MDn P4MDn P3DIRn P4DIRn 0 P3OUTn P4OUTn M Pin U ROUT, GOUT, BOUT, YMOUT (Digital output) 1 X P3INn P4INn DAROUT, DAGOUT, DABOUT, DAYMOUT (DAC output) Figure 11-9 P35/DAROUT/R, P36/DAGOUT/G, P37/DABOUT/B (Port 3), and P40/DAYMOUT/YM (Port 4)
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on 00: P25 01: SBI1,SBD1 10: TM4IOB 11: Reserved 0: Port input 1: Port output P2PUP5 P2MD10 P2MD11 00 10 P2DIR5 M 0: 3-line (SBI1,SBD1,SBT1) (PCNT0) bit 11 1: 2-line (SBD1,SBT1) SIFSEL1 U 01 X Pin 0: Port low output 1: Port high output 00 P2OUT5 M P25/ SBI1/ SBD1/ TM4IOB U 01 SBO1 TM4IOB output P2IN5 (PCNT0) bit 13 ODASCI1 X 10 0: Push-pull 1: Open-drain (For I2C mode) Schmidt trigger SBI1 0: Pullup off 1: Pullup on 00: P25 01: SB
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P5PUP5 0: P55 1: SBO0 P5MD5 0: Port input 1: Port output P5DIR5 (PCNT0) bit 12 ODASCI0 0: Push-pull 1: Open-drain (For I2C mode) SBO0 1 Pin M 0: Port low output 1: Port high output U P5OUT5 0 X P55/ SBO0 P5IN5 Schmidt trigger SBI0 0: Pullup off 1: Pullup on P5PUP6 0: P56 1: SBI0/SBD0 P5MD6 0: Port input 1: Port output 0 P5DIR6 M U 0: 3-line (SBI0,SBO0,SBT0) (PCNT0) bit 10 1: 2-line (SBD0,SBT0) SIFSEL0 1 X 1 SBO0 Pin M 0: Port
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P5PUP7 0: P57 1: SBT0 P5MD7 0: Port input 1: Port output P5DIR7 (PCNT0) bit 12 ODASCI0 SBT0 output 0: Push-pull 1: Open-drain (For I2C mode) 0: Port low outut 1: Port high output Pin P5OUT7 P5IN7 Schmidt trigger SBT0 input Figure 11-12 P57/SBT0 (Port 5) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 263 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P0PUP2 0: P02 1: SCL1 P0MD2 0: Port input 1: Port output P0DIR2 0: Port low output 1: Port high output Pin P0OUT2 0 M P02/ SCL1 U 1 SCL output X P0IN2 Schmidt trigger SCL input I2CSEL1 I2CSEL0 0: Pullup off 1: Pullup on P6PUP1 0: P61 1: SCL0 P6MD1 0: Port input 1: Port output P6DIR1 0: Port low output 1: Port high output Pin P6OUT1 0 M P61/ SCL0 U 1 X P6IN1 Schmidt trigger Figure 11-13 P02/SCL1 (Port 0) and P61/SCL0 (Port 6) P
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P0PUP1 0: P01 1: SDA1 P0MD1 0: Port input 1: Port output P0DIR1 Pin 0: Port low output 1: Port high output P0OUT1 0 P01/ SDA1 M U 1 SDA output X P0IN1 Schmidt trigger SDA input I2CSEL1 I2CSEL0 0: Pullup off 1: Pullup on P6PUP0 0 : P60 1 : SDA0 P6MD0 0: Port input 1: Port output P6DIR0 Pin 0: Port low output 1: Port high output P6OUT0 0 M P60/ SDA0 U 1 X P6IN0 Schmidt trigger Figure 11-14 P01/SDA1 (Port 1) and P60/SDA0 (Port 6)
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P3PUPn 0: P31,P32 1: CVBS0,CVBS1 P3MDn 0: Port input 1: Port output P3DIRn 0: Port low output 1: Port high output Pin P3OUTn P3INn CVBS0,CVBS1 Figure 11-15 P31/CVBS0 and P32/CVBS1 (Port 3) Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual 266 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P3PUPn 0: P30, P33 1: CLH, CLL P3MD2 P3MD3 0: Port input 1: Port output P3DIRn 0: Port low output 1: Port high output Pin P3OUTn P3INn CLH, CLL Figure 11-16 P30/CLH and P33/CLL (Port 3) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 267 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P3PUP4 0: P34 1: VREF P3MD4 0: Port input 1: Port output P3DIR4 0: Port low output 1: Port high output Pin P3OUT4 P34/VREF P3IN4 VREF Figure 11-17 P34/VREF (Port 3) Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual 268 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P4PUPn 0: Port input 1: Port output P4DIRn 0: P41,P42,P43 1: TM1IO,TM5IOA,TM5IOB P4MDn Pin 0: Port low output 1: Port high output 0 P4OUTn M U 1 TM1IO output, TM5IOA output, TM5IOB output X P4INn TM1IO input, TM5IOA input, TM5IOB output, HI0 Figure 11-18 P41/TM1IO, P42/TM5IOA, and P43/TM5IOB/HI0 (Port 4) 0: Port input 1: Port output P4DIR4 0: P44 1: TM5IC/HI1 P4MD4 Pin 0: Port low output 1: Port high output P44/ TM5IC/ HI1 P4OUT4
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P4PUP5 0: P45 1: OSDXI P4OUT5 0: Port input 1: Port output P4DIR5 To internal circuit P4IN5 Pin P45/OSDXO (0: Cut,1: Connect) LCCNT is the OSDXI/O oscillation control signal from the OSD.
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P4PUP7 0: P47 1: HSYNC P4MD7 0: Port input 1: Port output P4DIR7 0: Port low output 1: Port high output Pin P4OUT7 P47/HSYNC P4IN7 Schmidt trigger HSYNC Figure 11-21 P47/HSYNC (Port 4) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 271 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P5PUP0 0: P50 1: SYSCLK P5MD0 0: Port input 1: Port output P5DIR0 0: Port low output 1: Port high output P5OUT0 0 M Pin U SYSCLK or divided SYSCLK output 1 X P50/SYSCLK P5IN0 Figure 11-22 P50/SYSCLK (Port 5) Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual 272 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P5PUP1 0: P51 1: YS P5MD1 0: Port input 1: Port output P5DIR1 0: Port low output 1: Port high output 0 P5OUT1 M Pin U 1 YSOUT X P51/YS P5IN1 Figure 11-23 P51/YS (Port 5) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 273 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P5PUP2 0: P52 1: IRQ4/VI0 P5MD2 0: Port input 1: Port output P5DIR2 0: Port low output 1: Port high output Pin P5OUT2 P52/IRQ4/VI0 P5IN2 Schmidt trigger IRQ4/VI0 Figure 11-24 P52/IRQ4/VI0 (Port 5) Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual 274 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P5PUP3 0: Port low output 1: Port high output P5OUT3 0: Port input 1: Port output P5DIR3 Pin P53/ RST P5IN3/ NTGTRST Schmidt trigger Figure 11-25 P53/RST (Port 5) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 275 Panasonic
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I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P5PUP4 0: P54/IRQ5 1: IRQ5/VSYNC P5MD4 0: Port input 1: Port output P5DIR4 0: Port low output 1: Port high output Pin P5OUT4 P54/IRQ5/VSYNC P5IN4 Schmidt trigger IRQ5 VSYNC Figure 11-26 P54/IRQ5/VSYNC (Port 5) Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual 276 Panasonic
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I/O Ports I/O Port Control Registers 11.3 I/O Port Control Registers P0PUP–P5PUP: Ports 0–5 Pullup Resistor Control Registers x’00FFB0’–x’00FFB5’ P7PUP–P8PUP: Ports 7–8 Pullup Resistor Control Registers x’00FFB8’–x’00FFBA’ Bit: Do not activate the pullup resistors when the pins are in output mode. This will cause incorrect output voltage levels and increase power and current consumption.
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I/O Ports I/O Port Control Registers P0IN–P5IN: Ports 0–5 Input Registers P7IN–P8IN: Ports 7–8 Input Registers Bit: x’00FFD0’–x’00FFD5’ x’00FFD8’–x’00FFDA’ 7 6 5 4 3 2 1 0 PnIN7 PnIN6 PnIN5 PnIN4 PnIN3 PnIN2 PnIN1 PnIN0 Reset: Pin Pin Pin Pin Pin Pin Pin Pin R/W: R R R R R R R R P6IN: Port 6 Input Register Bit: x’00FFD6’ 7 6 5 4 3 2 1 0 0 0 0 0 0 0 P6IN1 P6IN0 Reset: 0 0 0 0 0 0 Pin Pin R/W: R R R R R R R R The PnIN registers contain t
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I/O Ports I/O Port Control Registers P0MD: Port 0 Output Mode Register Bit: 7 6 5 4 3 x’00FFF0’ 2 1 0 P0MD7 P0MD6 P0MD5 P0MD4 P0MD3 P0MD2 P0MD1 P0MD0 Reset: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W P0MD is an 8-bit access register.
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I/O Ports I/O Port Control Registers P1MD: Port 1 Output Mode Register Bit: 15 — 14 13 12 11 10 9 x’00FFF2’ 8 7 6 P1MD P1MD P1MD P1MD P1MD P1MD P1MD P1MD P1MD 14 13 12 11 10 9 8 7 6 5 4 — P1MD 4 3 2 — P1MD 2 1 0 — P1MD 0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R R/W P1MD is a 16-bit access register.
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I/O Ports I/O Port Control Registers P2MD: Port 2 Output Mode Register Bit: 15 — 14 13 12 11 10 9 x’00FFF4’ 8 P2MD P2MD P2MD P2MD P2MD P2MD P2MD 14 13 12 11 10 9 8 7 6 — P2MD 6 5 4 — P2MD 4 3 2 — P2MD 2 1 0 — P2MD 0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R R/W R R/W P2MD is a 16-bit access register.
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I/O Ports I/O Port Control Registers P3MD: Port 3 Output Mode Register Bit: 7 6 5 4 3 x’00FFF6’ 2 1 0 P3MD7 P3MD6 P3MD5 P3MD4 P3MD3 P3MD2 P3MD1 P3MD0 Reset: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W P3MD is an 8-bit access register. P3MD7: P37 output switch If you set this field to 1, select DABOUT or B in the RGBC bit of ODS1. 0: P37 1: DABOUT or B P3MD6: P36 output switch If you set this field to 1, select DAGOUT or G in the RGBC bit of ODS1.
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I/O Ports I/O Port Control Registers P4MD: Port 4 Output Mode Register Bit: 7 6 5 4 3 x’00FFF8’ 2 1 0 P4MD7 P4MD6 P4MD5 P4MD4 P4MD3 P4MD2 P4MD1 P4MD0 Reset: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W P4MD is an 8-bit access register. P4MD7: P47 function switch 0: P47/NHSYNC 1: NHSYNC P4MD6 This bit exists, but contains no function. P4MD5: P45 function switch To use P45 or P46, set the OSCSEL[1:0] field of OSD1 to b’00’.
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I/O Ports I/O Port Control Registers P5MD: Port 5 Output Mode Register Bit: 7 6 5 4 3 x’00FFFA’ 2 1 0 P5MD7 P5MD6 P5MD5 P5MD4 P5MD3 P5MD2 P5MD1 P5MD0 Reset: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W P5MD is an 8-bit access register. P5MD7: P57 output switch To use SBT0 as an input pin, set this field to 0 and set the P5DIR7 bit to 0. 0: P57 1: SBT0 P5MD6: P56 output switch If you set this bit to 1, select SBI0 or SBD0 in the bit 10 of PCNT0.
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I/O Ports I/O Port Control Registers PCNT0: Port Control Register 0 Bit: 15 14 13 12 11 SCLK SCLK OD OD SIF F1 F0 ASCI1 ASCI0 SEL1 x’00FF90’ 10 9 8 SIF SEL0 I2C SEL1 I2C SEL0 7 6 5 4 3 2 OSD PLL ADC1 ADC0 HCNT RMC POFF POFF ON ON OFF OFF 1 0 VBI1 OFF VBI0 OFF Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PCNT0 is a 16-bit access register.
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I/O Ports I/O Port Control Registers OSDPOFF: OSD circuit enable To turn off the OSD block to save power: 1. Write a 0 to OSD (OSD1, bit 10). 2. Wait for the next VSYNC input. 3. Write a 0 to OSDPOFF (PCNT0, bit 7), turning the clock off. If you turn the clock off before the VSYNC input, power usage may not drop or the microcontroller may halt. Setting this bit to 0 shuts off the system clock supply to the OSD block, reducing power dissipation.
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I/O Ports I/O Port Control Registers PCNT2: Port Control Register 2 Bit: 15 — 14 — 13 — 12 — 11 — 10 — x’00FF92’ 9 8 — P7P8 CNT 7 6 5 4 3 2 I2C OFF (Test Bits) 1 0 PWM OSD OFF REGE Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W P7P8CNT: Ports 7 and 8 forced pullup Always set bits 7 to 3 of PCNT2 to 0. Ports 7 and 8 are only available in the quad flat package.
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ROM Correction Description 12 ROM Correction 12.1 Description The ROM correction function can correct the program data in any address within the 256-kilobyte ROM. (It cannot correct OSD ROM data.) A maximum of sixteen addresses can be corrected. Addresses are set as address match interrupts. This function shortens time-to-market for large-scale designs, since changes can be implemented in the software after the mask ROM is complete. The ROM correction function has numerous other applications.
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ROM Correction Block Diagram 12.2 Block Diagram Figure 12-3 is a block diagram of the ROM correction circuit. A match detection circuit constantly monitors the ROM address specified by the CPU instruction pointer (IP). When the value matches a correction address, the circuit replaces the data output from the ROM with the data in the appropriate correction data register. It then sends the corrected data to the CPU.
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ROM Correction ROM Correction Control Registers 12.4 ROM Correction Control Registers Table 12-1 shows the organization of the address match and data registers for ROM correction. Write a ROM address to be corrected to an AMCHIHn and AMCHILn register pair and write the corrected data to the associated CHDATn register. Enable ROM correction for the associated address in the ROMCEN register.
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ROM Correction ROM Correction Control Registers ROMCEN12: Address 12 ROM correction enable 0: Disable 1: Enable ROMCEN11: Address 11 ROM correction enable 0: Disable 1: Enable ROMCEN10: Address 10 ROM correction enable 0: Disable 1: Enable ROMCEN9: Address 9 ROM correction enable 0: Disable 1: Enable ROMCEN8: Address 8 ROM correction enable 0: Disable 1: Enable ROMCEN7: Address 7 ROM correction enable 0: Disable 1: Enable ROMCEN6: Address 6 ROM correction enable 0: Disable 1: Enable ROMCEN5: Address
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ROM Correction ROM Correction Control Registers AMCHIH0–AMCHIHF: ROM Correction Address Match Register n (High) Bit: 7 6 5 4 3 2 1 0 CHAD 23 CHAD 22 CHAD 21 CHAD 20 CHAD 19 CHAD 18 CHAD 17 CHAD 16 Reset: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W AMCHIHn is an 8-bit access register.
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I 2 C Bus Controller Description 13 I 2 C Bus Controller 13.1 Description The MN102H75K/85K contains one I2C bus controller, fully compliant with the I2C specification, that can control one of two I2C bus connections. An I2C bus is a simple, two-wire bus for transferring data between ICs. Since it requires only two lines, a serial data line (SDA) and a serial clock line (SCL), it minimizes interconnections so ICs have fewer pins and there are less PCB tracks. The result is smaller and less expensive PCBs.
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I 2 C Bus Controller Description Figure 13-2 shows an example of an I 2C bus configuration using two microcontrollers. Both I2C bus lines, SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pullup resistor. The open-drain output pins of the microcontrollers perform the wired-AND function on the bus. The software controls when each microcontroller operates as a transmitter or receiver, or whether is in master or slave mode.
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I 2 C Bus Controller Description Figure 13-3 shows the MN102H75K/85K operation sequence in each of these modes. In all modes, the I2C bus controller generates an interrupt after each data byte transfer, then the software loads the next data byte. Interrupt MN102H51K Master S Interrupt Interrupt R/W = 0 Address R/W (7 bits) Slave Data (8 bits) ACK Data (8 bits) ACK P ACK Normally ACK = 0 A. Master Transmitter ACK = 1 signals transfer end to slave transmitter.
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I 2 C Bus Controller Block Diagram 13.
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I 2 C Bus Controller Functional Description ■ Register settings conversions to I2C protocol The I2C bus controller converts the data in the I2CDTRM register to the I2C protocol. ■ Transfer modes changes A write to the I2CDTRM register indicates the transfer mode (master transmitter/ receiver or slave transmitter/receiver) for a new transfer. To minimize software control, the hardware generates an interrupt each time a transfer ends.
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I 2 C Bus Controller Setting Up the I 2 C Bus Connection 13.4 Setting Up the I 2 C Bus Connection Set the I2C connection in the I2CSEL0 and I2CSEL1 bits of the PCNT0 register (x’00FF90’). Since the SCL0, SDA0, SCL1, and SDA1 pins also serve as general-purpose port pins, and reset to the general-purpose function, you must set these bits every time the program uses the I2C function. You must also select the I2C function in the port mode registers.
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I 2 C Bus Controller SDA and SCL Waveform Characteristics 13.5 SDA and SCL Waveform Characteristics Figure 13-6 and table 13-5 provide the timing definitions and specifications for the for the MN102H75K/85K I2C bus interface.
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I 2 C Bus Controller 2 I C Interface Setup Examples 13.6 I 2 C Interface Setup Examples 13.6.1 Setting Up a Transition from Master Transmitter to Master Receiver This example demonstrates how to set up a data transfer when changing from master transmitter to master receiver. Figure 13-7 shows an example waveform. 13.6.1.
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I 2 C Bus Controller I 2 C Interface Setup Examples 13.6.1.3 Setting Up the Second Interrupt When the microcontroller receives the data x’85’ from the slave device, it returns an ACK = 0 signal and the I2C bus controller generates an interrupt. At this point, implement the following settings: ■ To set up the interrupt: Set the I2C0ICH and I2C0ICL register pair (x’00FC9C’) to x’0100’. This enables I2C interrupts and clears the previous interrupt request. ■ To set up the I2C registers: 1.
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I 2 C Bus Controller 2 I C Interface Setup Examples 13.6.2 Setting Up a Transition from Slave Receiver to Slave Transmitter This example demonstrates how to set up a data transfer when changing from slave receiver to slave transmitter. Figure 13-8 shows an example waveform. 13.6.2.
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I 2 C Bus Controller I 2 C Interface Setup Examples 13.6.2.3 Setting Up the Second Interrupt The master sends an ACK = 0 signal, so the microcontroller must send the next data byte. Set up the transmission data as follows: ■ To set up the interrupt: Set the I2C0ICH and I2C0ICL register pair (x’00FC9C’) to x’0100’. This enables I2C interrupts and clears the previous interrupt request. To set up the I2C registers: ■ 1. Read the I2CDREC register (x’007E42’) to determine the I2C bus controller status.
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I 2 C Bus Controller 2 I C Bus Interface Registers 13.7 I 2 C Bus Interface Registers All registers in I2C blook cannot be written by byte (by word only). Read by byte is possible.
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I 2 C Bus Controller I 2 C Bus Interface Registers I2CDREC: I2C Reception Data Register Bit: 15 — 14 13 MODE MODE 1 0 x’007E42’ 12 11 10 9 8 7 6 5 4 3 2 1 0 STS LRB AAS LAB BB D7 D6 D5 D4 D3 D2 D1 D0 Reset: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R The I2CDREC register contains the status bits for monitoring the device and the reception data. I2CDREC is a read-only register.
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I 2 C Bus Controller 2 I C Bus Interface Registers I2CCLK: I2C Clock Control Register Bit: x’007E46’ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W C[9:0]: Output clock frequency select This 10-bit field determines the SCL output.
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H Counter Description 14 H Counter 14.1 Description The MN102H75K/85K contains two H counter circuits that can be used to count the HSYNC signal. Each H counter consists of a 10-bit counter and 10-bit register. 14.2 Block Diagram Selected in SELR[20:00]/SELR[21:01] fields of HCCNT0/HCCNT1 registers. VI0 VSYNC Selected in REDG0/REDG1 bits of HCCNT0/HCCNT1 registers.
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H Counter H Counter Operation Figure 14-3 shows the input timing for the count source and reset signals. Never input a count source signal in less than 245 ns (t1) after the reset signal input. Otherwise, the signal may be counted as part of the previous count cycle. HI0 counted on the rising edge HI0 t1 t2 t 1 ≥ 245 ns t 2 ≥ 200 ns VI0 VSYNCcounted on the falling edge Note: In this example, HI0 is active high and VSYNC is active low.
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H Counter H Counter Operation The H counter counts the HSYNC signal for the interval set in the HCCNT0 (x’007EB0’) or HCCNT1 (x’007EB2’) register, latches the count value in the 10bit register, then clears the counter.
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H Counter H Counter Control Registers 14.4 H Counter Control Registers All registers in H Counter block cannot be written by byte (by word only). Read by byte is possible.
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H Counter H Counter Control Registers HCD0: H Counter Data Register 0 Bit: 15 — 14 — 13 — 12 — 11 — x’007EB4’ 10 9 8 7 6 5 4 3 2 1 0 — HCD 90 HCD 80 HCD 70 HCD 60 HCD 50 HCD 40 HCD 30 HCD 20 HCD 10 HCD 00 Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R HCD[90:00]: Count from HI0 source signal This field stores the HI0 clock source count. It becomes x’3FF’ on overflow.
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Register Map Appendix A Register Map Table A-1 Register Map: x’007E00’ to x’007FFF’ (Registers in this area cannot be written by byte only by word.
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Register Map Table A-2 Register Map: x’00FC00’ to x’00FDFF’ 20 4 LSBs MSBs F E D C B A 9 8 7 00FC00 6 5 4 3 2 IAGR 1 0 CPUM Description Special function registers 00FC10 00FC20 00FC30 00FC40 IQ1 ICH IQ1 ICL IQ0 ICH IQ0 ICL 00FC50 IQ5 ICH IQ5 ICL IQ4 ICH IQ4 ICL EI ICR VBIW VBIW ICH ICL 00FC70 ADM0 ADM0 ADM1 ADM1 ADM2 ADM2 ADM3 ADM3 RMC RMC ICH ICL ICH ICL ICH ICL ICH ICL ICH ICL TM3UD TM3UD ICH ICL 00FC80 I2C ICH 00FC90 I2C ICL VBIV W ICH VBIV W ICL WD ICR IQ3 ICH 00FC60 TM
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Register Map Table A-3 Register Map: x’00FE00’ to x’00FFFF’ 20 4 LSBs MSBs F E D C B A 9 8 7 6 5 4 00FE00 00FE10 00FE20 3 2 1 0 TM3 BC TM3 BR TM3 MD TM2 BC TM2 BR TM2 MD TM1 BC TM1 BR TM1 MD TM0 BC TM0 BR TM0 MD Description 8-bit timer registers TM8TST (test register) 00FE30 00FE40 00FE50 00FE60 00FE70 00FE80 TM4TST (test register) 00FE90 TM5TST (test register) (TM4CBX ) (TM5CBX ) (TM4CAX ) (TM5CAX TM5CB ) TM4CB TM4CA TM4BC TM4MD 16-bit timer 4 registers TM5CA TM5BC TM5MD 16-bi
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Register Map MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company 315 Panasonic
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MN102HF75K Flash EEPROM Version Description Appendix B MN102HF75K Flash EEPROM Version B.1 Description The MN102HF75K and MN102HF85K are electrically programmable, 256kilobyte flash ROM versions of the MN102H75K and MN102H85K. They are programmed in one of two modes: ■ PROM writer mode, which uses a dedicated adaptor socket and writer. In this mode, the user program can occupy the entire 256-kilobyte ROM space.
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MN102HF75K Flash EEPROM Version Benefits B.2 Benefits Because you can maintain and upgrade the program in the MN102HF75K/85K up to and immediately following product release, this version of the device shortens time-to-market by as much as one month. This device is ideal for applications in quickly changing markets, since it allows you to revise the microcontroller program in an existing product. B.
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MN102HF75K Flash EEPROM Version Using the PROM Writer Mode Table B-2 PROM Writer Hardware Device Hardware Part MN102HF75KBF MN102HF85KDP 84-pin QFP 64-pin SDIP Package (external view) Installed in Adaptor Installed in M Panasonic M Panasonic Set this switch to the right. Ordering information: Ordering information: Part no.: FLS84F18--102HF57 Part no.: FLS64SD-102HF51 OEM: Matsushita Electric Industrial Co., Ltd. OEM: Matsushita Electric Industrial Co., Ltd.
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MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4 Using the Onboard Serial Programming Mode The serial programming mode is primarily used to program the flash ROM in devices that are already installed on a PCB board. Panasonic provides the dedicated hardware and software for this mode. This section describes the microcontroller hardware, system configuration, software register map, and protocol for this type of programming operation.
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MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4.1 Configuring the System for Onboard Serial Programming AC adaptor Target board power source VDD Target board IC card IC card Serial writer (AF200 flash microcontroller programmer (provisional)) Figure B-5 Serial Writer Hardware Setup The workstation containing the program data sends the program to the serial writer through an IC card.
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MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4.2 Circuit Requirements for the Target Board Target board VPP = +5 V VDD VDD (for level detection) 10 kΩ RST Serial writer RST SBT VPP SBT1 MCU SBD External power source 3.0 V - 3.3 V SBD1 GND GND Figure B-6 Target Board–Serial Writer Connection Table B-3 Pin Descriptions for Target Board–Serial Writer Connection Pin Name Description VPP 5-V power supply VDD 3.0–3.
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MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4.3 Microcontroller Hardware Used in Onboard Serial Programming B.4.3.
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MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4.4 Microcontroller Memory Map Used During Onboard Serial Programming B.4.4.
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MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode ■ Branch instruction to interrupt service routine Normally, interrupt servicing starts at address x’0x80008’, but the soft branch instruction in the serial writer load program branches to x’0x82018’. This address must hold a JMP instruction pointing to the real start address for the interrupt service routine. ■ User program area This area stores the user program. B.4.4.
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MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4.6 Setting Up the Onboard Serial Programming Mode To enter serial programming mode, the microcontroller must be in write mode. This section describes the pin setup for the serial writer interface. Normal timing waveform A B C D VDD VPP RST SBT SBD Timing waveform during serial programming VDD VPP RST SBT SBD t1 t2 t3 Figure B-8 Timing for the Serial Writer Interface ■ To set up the serial writer interface: 1.
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MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode ■ Start routine for the load program Reset start SBT pin == high && SDB pin == low? No Yes Wait tWAIT1 SBT pin == high && SDB pin == low? No Yes Has tWAIT2 passed? Yes No No SBT pin == high && SDB pin == high? Yes Start serial writer load program Execute user program Figure B-9 Load Program Start Flow Conditions: 1. After the load program initiates a reset start, SBD must be low and SBT high. 2.
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MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4.7 Branching to the User Program B.4.7.1 Branching to the Reset Start Routine Reset start Serial writer? No Yes Start serial writer load program Branch to address x’82010’ Execute user program (Generate 10-cycle delay) Figure B-10 Flow of Branch to Reset Start Routine When the reset starts, the serial writer load program initializes only if SBD is low.
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MN102HF75K Flash EEPROM Version Reprogramming Flow B.5 Reprogramming Flow Figure B-12 shows the flow for reprogramming (erasing and programming) the flash memory. Write 0s to entire memory Erase Erase routine Reverse Write user program Figure B-12 EEPROM Programming Flow Always program after erasing is completed.Erasing is sometimes not done finely,even though PROMwriter or onboard serial writer shows “PASS“in blank check. And in that situation the data programed successfully may be incorrect.
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MN102H75K/F75K/85K/F85K LSI User's Manual Description Record of Changes (Ver.1.0 to 1.
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MN102H75K/F75K/85K/F85K LSI User’s Manual Modified Points From MN102H75K/F75K To MN102H75K/F75K/85K/F85K page P16 Before Modify page P16 This manual is intended for assembly-language programming engineers. It describes the internal configuration and hardware functions of the MN102H75K microcontrollers. Using This Manual The chapters in this manual deal with the internal blocks of the MN102H75K.
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P30 1.6 Pin Descriptions 1.6.
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P33 The MN102H75K contains an internal PLL circuit. To use this circuit, you must connect it to an external (lag-lead) filter. P34 The MN102H75K/85K contains an internal PLL circuit. To use this circuit, you must connect it to an external (lag-lead) filter. P37 The most important factor in real-time control is an MCU’s speed in servicing interrupts.
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P77 The MN102H75K contains four 8-bit timers that can serve as interval timers, event timer/counters, clock generators (divide-by-2 output of the underflow), reference clocks for the serial interfaces, or start timers for A/D conversions. The clock source can be the internal clock (oscillator frequency divided by 2) or the external clock (1/4 or less the oscillator frequency input).
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P307 The MN102H75K contains two H counter circuits that can be used to count the HSYNC signal. Each H counter consists of a 10-bit counter and 10-bit register P307 P308 The MN102H75K/85K contains two H counter circuits that can be used to count the HSYNC signal. Each H counter consists of a 10-bit counter and 10-bit register P308 Table 14-1 H Counter Pins Table 14-1 H Counter Pins Pin No. Pin No.
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MN102H75K/F75K/85K/F85K LSI User’s Manual October,2001 1st Edition 1st Printing Issued by Matsushita Electric Industrial Co., Ltd.  Matsushita Electric Industrial Co., Ltd.
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Semiconductor Company, Matsushita Electric Industrial Co., Ltd. Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.panasonic.co.jp/semicon/ SALES OFFICES ■ NORTH AMERICA ●U.S.A. Sales Office: Panasonic Industrial Company [PIC] • New Jersey Office: Two Panasonic Way Secaucus, New Jersey 07094 U.S.A. Tel: 1-201-348-5257 Fax:1-201-392-4652 • Chicago Office: 1707 N. Randall Road Elgin, Illinois 60123-7847 U.S.A.