Data Sheet

Confidential and Proprietary of Luxshare-ict Electronic Technology (KUNSHAN) Ltd. ， which are not permitted to
disclose to others and shall not be distributed, reproduced, or disclosed
LS005ONWCS
Datasheet
 PCM Timing Specification Data—Master Mode
Symbol Parameter Condition Min Typ Max Units
F
BCLK
Bit clock frequency -- -- 2/2.048 -- MHz
Duty Cycle
BCLK
Bit clock duty cycle -- 0.4 0.5 0.6 --
T
BCLK rise/fall
PCM_CLK rise/fall time -- -- 3 -- ns
T
DO
Delay from PCM_CLK rising edge to
PCM_DOUT rising edge
-- -- -- 15 ns
T
DISU
Setup time for PCM_DIN before
PCM_CLK falling edge
-- 20 -- -- ns
T
DIHO
Hold time for PCM_DIN after
PCM_CLK falling edge
-- 15 -- -- ns
T
BF
Delay from PCM_CLK rising edge to
PCM_SYNC rising edge
-- -- -- 15 ns
PCM Timing Specification Diagram for PCM_SYNC Signal—Master Mode