Data Sheet

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LS005ONWCS
Datasheet
7.3.2 PCM Timing Diagram—Slave Mode
 PCM Timing Specification Data—Slave Mode
Symbol Parameter Condition Min Typ Max Units
FBCLK Bit clock frequency -- -- 2/2.048 -- MHz
Duty Cycle
BCLK
Bit clock duty cycle -- 0.4 0.5 0.6 --
TBCLK rise/fall PCM_CLK rise/fall time -- -- 3 -- ns
TDO
Delay from PCM_CLK rising
edge to PCM_DOUT rising edge
-- -- -- 30 ns
TDISU
Setup time for PCM_DIN
before PCM_CLK falling edge
-- 15 -- -- ns
PCM Timing Specification Diagram for Data Signals—Slave Mode
PCM Timing Specification Diagram for PCM_SYNC Signal—Slave Mode