User Manual

Operational Overview
AES16e User Manual
Page 36
5.2.1 Sample Clock Sources
The sample clock generator can derive its reference clock from both an internal and various external
sources. Only one source can be selected at any given time. User control of the sample clock source
selector is provided on the Adapter window of the Lynx Mixer application. The available clock sources are:
 On-board low-jitter oscillator (Internal)
 External Clock In: signal from the CLOCK IN BNC connector on the CBL-AES1604 break-out cable
 Header Clock In: signal from the board-mounted header connector
 LStream Port In: word-clock from an LStream device connected to the LStream header port
 Digital In 1- 4: word-clock recovered from one of the first AES-3 inputs
5.2.2 Phase-lock Loops and Clock Dividers
A two-stage phase-lock loop system is used to generate a high-frequency PLL Clock while attenuating jitter
in the selected sample clock source. Refer to the Section 5.3 SynchroLock™ for a description of the
operation of the PLL’s. Clock dividers derive required system clocks from the PLL clock.
5.3 SynchroLock™
The AES16e incorporates SynchroLock clock synchronization technology to provide extreme tolerance to
noisy external AES/EBU and word-clock signals while generating an ultra-low jitter clock. This technology
is especially useful for combating noise induced on cables in complex studio installations. SynchroLock
provides clock synchronization while insuring bit-perfect digital transmission. When the AES16e is
connected in an AES/EBU daisy chain, SynchroLock acts like a jitter firewall to prevent the propagation of
jitter to downstream devices.
By coupling statistical analysis with low-noise clock generation techniques, SynchroLock is capable of
attenuating jitter on incoming AES/EBU signals by a factor of 3000:1. Compare this to attenuation of 100:1
or less for professional quality analog phase-lock loops (PLL). SynchroLock can easily handle AES/EBU
signals with jitter levels in excess of 800 nanoseconds.
The SynchroLock sample clock is a two-stage system that is comprised of a fast-locking, wide-range
analog PLL and digitally controlled crystal-based secondary stage. Due to extensive number crunching of
the secondary stage, SynchroLock typically requires one to two minutes to achieve final lock. While the
secondary stage is working, the analog PLL loop maintains lock, but with much less jitter attenuation than
the secondary stage.
When the final lock state is achieved, the secondary stage is switched on line and becomes the system clock
source. In some cases this switching process may cause a momentary disruption in digital I/O. Because of
this, it is recommended that recording or playback not be started until the green LOCK indicator in the
SynchroLock status window is observed. This status window is located on the Adapter window of the Lynx
Mixer.
SynchroLock works on any external word-clock signal. By default, SynchroLock is active when the
Sample Clock source is set to a clock source other than Internal.
SynchroLock can be disabled in the settings menu of the mixer by clicking on “Settings > Advanced >
SynchroLock,” but this is not recommended.
SynchroLock is capable of locking to word-clock frequencies within +/- 100ppm of 44.1 kHz, 48 kHz,
88.2kHz, 96 kHz, 176.4 kHz, or 192 kHz. Signals that fall outside of the lock range will cause the red
RANGE indictor to appear in the SynchroLock status window. In this case, the analog PLL is active and
will source the system sample clock.