User Manual
Operational Overview
rate limited: at sample rates of 176.4 kHz or 192 kHz, there are up to 4 sources per output. The benefits of
this architecture include the ability to:
Route any input to any or all outputs
Route any play device data from an application to any or all outputs
Mix any input with any play device for recording monitoring
Create sub mixes for digital effect sends
Since all mixing and routing is hardware-based, so called “zero latency” is achieved.
Software control of the digital mixer outputs is provided in the Outputs window of the Lynx Mixer
application. The Monitor Select function in the diagram corresponds to the Output Monitor Source buttons
in the Mixer. The volumes controls for the submixer inputs are below these buttons. The master fader on
the Outputs window of the Mixer adjusts all of the submixer input volumes. Mute and dither controls are
also provided for each channel on this window. The dither button enables the output TPDF dither.
5.1.6 Physical Outputs
The physical outputs of the AES16e include eight AES3 signals and the output of the LStream port. As
shown in Figure 6, the 16 channels of the Output Bus derived from the output submixers feed the physical
outputs. Since there are 16 physical outputs (16 AES3) and up to 32 signals on the Output Bus (including
16 LStream channels), data sent to the 16 play devices is mirrored on the LStream and AES-3 outputs.
An AES-3 transmitter followed by an isolation transformer converts Output Bus signals to AES-3 signals.
An LStream transmitter formats data for the LStream output port. To provide more routing flexibility the
“1-8 / 9-16 Select” function shown in the diagram allows routing of output signals to a bank of eight
LStream channels. Output Bus signals 1-8 can be routed to LStream channels 9-16 if desired.
5.2 Sample Clock Generator
The AES16e utilizes a master sample clock generator to derive all clocks related to the digital audio
sampling rate. As shown in Figure below, the sample clock generator provides a selection of various
clocks sources ands both a wide range and SynchroLock phase-lock loop (PLL).
Figure 7: Sample Clock Generator
AES16e User Manual
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