Datasheet

RTL8169S-32/RTL8169S-64
Datasheet
Integrated Gigabit Ethernet Controller 18 Track ID: JATR-1076-21 Rev. 1.4
Registers. Software can read and write to the EEPROM using “bit-bang” accesses via the 9346CR Register. The interface
consists of EESK, EECS, EEDO, and EEDI.
Table 10. Flash/EEPROM Interface
Flash Description
MA[16:0]
(PCIAD16:0)
Boot PROM Address Bus. These pins are used to access up to a 128k-byte flash
memory or EEPROM.
MD7-0(PCIAD31:24) Boot PROM data bus when in Boot PROM mode.
CSB(EECS/BROMCSB) The chip select signal of the Boot PROM.
OEB(LED0/BROMOEB) Enables the output buffer of the Boot PROM or Flash memory during a read
operation.
EEPROM Description
EECS 93C46 (93C56) chip select
EESK EEPROM serial data clock
EEDI/Aux Input data bus/Input pin to detect if Aux. Power exists or not on initial power-on.
This pin should be connected to Boot PROM. To support wakeup from ACPI
D3cold or APM power-down, this pin must be pulled high to aux. power via a
resistor. If this pin is not pulled high to Aux. Power, the RTL8169S assumes that no
Aux. Power exists.
EEDO Output data bus
6.7. Power Management
The RTL8169S is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and Network Device Class
Power Management Reference Specification (V1.0a), such as to support an OS-directed Power Management (OSPM)
environment.
The RTL8169S can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via
PME# when such a packet or event occurs. Then, the whole system can be restored to a normal state to process incoming jobs.
When the RTL8169S is in power down mode (D1 ~ D3):
• The Rx state machine is stopped, and the RTL8169S monitors the network for wakeup events such as a Magic Packet,
Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power down mode, the RTL8169S will not
reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx FIFO buffer.
• The FIFO status and packets that have already been received into the Rx FIFO before entering power down mode are held
by the RTL8169S.
• Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held.
• After restoration to a D0 state, the RTL8169S transfers data that was not moved into the Tx FIFO buffer during power down
mode. Packets that were not transmitted completely last time are re-transmitted.