Datasheet

RTL8169S-32/RTL8169S-64

Datasheet

Integrated Gigabit Ethernet Controller 26 Track ID: JATR-1076-21 Rev. 1.4

7.7.2. PCI Clock Specification

0.6Vcc

0.2Vcc

0.4Vcc, peak-to-peak

(minimum)

0.3Vcc

T_high T_low

T_cyc

0.5Vcc

0.4Vcc

Figure 10. 3.3V Clock Waveform

CLK (@ Device #1)

CLK (@ Device #2)

T_skew

V_ih

V_il

V_test

Figure 11. Clock Skew Diagram

Table 19. Clock and Reset Specifications

66MHz 33MHz

Symbol Parameter Min Max Min Symbol Parameter

Tcyc CLK Cycle Time 15 30 30 ∞ ns

Thigh CLK High Time 6 11 ns

Tlow CLK Low Time 6 11 ns

-- CLK Slew Rate 1.5 4 1 4 V/ns

-- RST# Slew Rate 50 - 50 - mV/ns

Tskew CLK Skew 1 2 ns