Datasheet

RTL8169S-32/RTL8169S-64
Datasheet
Integrated Gigabit Ethernet Controller vi Track ID: JATR-1076-21 Rev. 1.4
List of Figures
FIGURE 1. 128-PIN QFP PIN ASSIGNMENTS ............................................................................................................................... 3
FIGURE 2. 233-PIN TFBGA PIN ASSIGNMENTS.......................................................................................................................... 4
FIGURE 3. RX LED .................................................................................................................................................................. 14
FIGURE 4. TX LED................................................................................................................................................................... 15
FIGURE 5. TX/RX LED ............................................................................................................................................................ 16
FIGURE 6. LINK/ACT LED ..................................................................................................................................................... 17
FIGURE 7. SERIAL EEPROM INTERFACE TIMING..................................................................................................................... 23
FIGURE 8. OUTPUT TIMING MEASUREMENT CONDITIONS ........................................................................................................ 25
FIGURE 9. INPUT TIMING MEASUREMENT CONDITIONS ............................................................................................................ 25
FIGURE 10. 3.3V CLOCK WAVEFORM ........................................................................................................................................ 26
FIGURE 11. CLOCK SKEW DIAGRAM .......................................................................................................................................... 26
FIGURE 12. I/O READ................................................................................................................................................................. 27
FIGURE 13. I/O WRITE ............................................................................................................................................................... 27
FIGURE 14. CONFIGURATION READ............................................................................................................................................ 28
FIGURE 15. CONFIGURATION WRITE .......................................................................................................................................... 28
FIGURE 16. BUS ARBITRATION................................................................................................................................................... 29
FIGURE 17. MEMORY READ BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT) .......................................................... 29
FIGURE 18. MEMORY WRITE BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT)......................................................... 30
FIGURE 19. TARGET INITIATED TERMINATION - DISCONNECT ................................................................................................... 30
FIGURE 20. TARGET INITIATED TERMINATION - ABORT ............................................................................................................ 31
FIGURE 21. MASTER INITIATED TERMINATION - ABORT............................................................................................................ 31
FIGURE 22. PARITY OPERATION – ONE EXAMPLE...................................................................................................................... 32
FIGURE 23. MEMORY READ BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT)......................... 33
FIGURE 24. MEMORY WRITE BELOW 4GB (32-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT)........................ 34
FIGURE 25. MEMORY READ BELOW 4GB (32-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ......................... 35
FIGURE 26. MEMORY WRITE BELOW 4GB (32-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT)........................ 36
FIGURE 27. MEMORY READ ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT) ................................................ 37
FIGURE 28. MEMORY WRITE ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA; 32-BIT SLOT)............................................... 37
FIGURE 29. MEMORY READ ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ............... 38
FIGURE 30. MEMORY WRITE ABOVE 4GB (DAC, 64-BIT ADDRESS, 32-BIT DATA TRANSFER GRANTED; 64-BIT SLOT).............. 39
FIGURE 31. MEMORY READ ABOVE 4GB (DAC, 64-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT) ............... 40
FIGURE 32. MEMORY WRITE ABOVE 4GB (DAC, 64-BIT ADDRESS, 64-BIT DATA TRANSFER GRANTED; 64-BIT SLOT).............. 41