F28M35H52C, F28M35H22C, F28M35M52C, F28M35M22C, F28M35M20B, F28M35E20B Concerto MCUs Silicon Errata Literature Number: SPRZ357J August 2011 – Revised July 2014
Contents 1 2 3 4 Introduction ......................................................................................................................... Device and Development Support Tool Nomenclature .............................................................. Device Markings .................................................................................................................. Usage Notes and Known Design Exceptions to Functional Specifications .................................. 4.1 4.
www.ti.com List of Figures 1 Example of Device Markings ............................................................................................... 5 2 Example of Device Nomenclature ......................................................................................... 5 List of Tables 1 2 3 4 5 6 ................................................................... 5 List of Usage Notes..........................................................................................................
Silicon Errata SPRZ357J – August 2011 – Revised July 2014 F28M35x Concerto™ MCU Silicon Errata 1 Introduction This document describes the silicon updates to the functional specifications for the F28M35x microcontrollers (MCUs).
Device Markings www.ti.com 3 Device Markings Figure 1 provides an example of the Concerto device markings and defines each of the markings. The device revision can be determined by the symbols marked on the top of the package as shown in Figure 1. Some prototype devices may have markings different from those illustrated. Figure 2 shows an example of the device nomenclature.
Usage Notes and Known Design Exceptions to Functional Specifications 4 www.ti.com Usage Notes and Known Design Exceptions to Functional Specifications NOTE: For errata relating to the Cortex-M3 r2p0 core, see the ARM Core Cortex-M3 / Cortex-M3 with ETM (AT420/AT425) Errata Notice at the ARM Ltd. website. 4.1 Usage Notes Usage notes highlight and describe particular situations where the device's behavior may not match presumed or documented behavior.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com 4.1.2 EPI: New Feature Addition to EPI Module Usage Note Revision(s) Affected: A, B In the EPI module, many new features have been added on silicon revisions A and onwards. New configuration registers have been added to enable new features.
Usage Notes and Known Design Exceptions to Functional Specifications 4.1.5 www.ti.com Major Device Revision Usage Note Revision(s) Affected: 0 There were significant changes to the device functionality between Revision 0 and Revision A. Code developed on the revision 0 device may not operate as expected on later revisions.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com 4.2 Known Design Exceptions to Functional Specifications Table 4. Table of Contents for Advisories Title ...................................................................................................................................... Advisory — Analog Subsystem: Analog Subsystem Function InitAnalogSystemClock() is Incomplete .....................
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Table 4. Table of Contents for Advisories (continued) is a Nested NMI ................................................................................................................ Advisory — Master Boot ROM: NMI Handler Not Executed if NMI Occurs at Power Up or Immediately After a Reset .. Advisory — Master Boot ROM: Parallel Boot Mode Will Not Work as Intended ................................................
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Table 5 shows which silicon revision(s) are affected by each advisory. Table 5.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Table 5.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory Analog Subsystem: Analog Subsystem Function InitAnalogSystemClock() is Incomplete Revision(s) Affected 0, A, B Details The factory function InitAnalogSystemClock() is provided for the purpose of configuring the clock ratio used by the Analog Subsystem and returning its status. A successful, properly configured device will return the success code 0xA005.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory Analog Subsystem: Potential Race Condition after Executing Analog Subsystem Functions AnalogClockEnable() or AnalogClockDisable() Revision(s) Affected 0, A, B Details The factory functions AnalogClockEnable() and AnalogClockDisable() are provided for the purpose of configuring the peripheral clocks of the analog modules. When an analog clock configuration attempt succeeds, the function returns the value of 0.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory ADC: Initial Conversion Revision(s) Affected 0, A, B Details When the ADC conversions are initiated by any source of trigger in either sequential or simultaneous sampling mode, the first sample may not be the correct conversion result. Workaround(s) For sequential mode, discard the first sample at the beginning of every series of conversions.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory ADC: Offset Self-Recalibration Requirement Revision(s) Affected 0, A, B Details The factory offset calibration from Device_cal() may not ensure that each ADC's offset remains within specifications under all operating conditions in the customer's system.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory UART: RTRIS Bit in the UARTRIS Register is Only Set When the Interrupt is Enabled Revision(s) Affected 0, A, B Details The RTRIS (UART Receive Time-Out Raw Interrupt Status) bit in the UART Raw Interrupt Status (UARTRIS) register should be set when a receive time-out occurs, regardless of the state of the RTIM enable bit in the UART Interrupt Mask (UARTIM) register.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory HWBIST: C28x HWBIST Should Not be Used Revision(s) Affected 0, A, B Details Using the HWBIST feature on the C28x CPU can cause unpredictable behavior in the C28x subsystem. The HWBIST feature on Cortex-M3 is supported with no issues. Workaround(s) None. The C28x HWBIST should not be used on the revisions affected.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory Cortex-M3 Flash: C28x Reset While C28x Holding Pump Ownership Can Cause Erroneous Cortex-M3 Flash Reads Revision(s) Affected 0, A, B Details If the C28x Subsystem is reset while it owns the flash pump semaphore, then the flash pump itself will also reset. Since the flash pump is also used by the Cortex-M3 Subsystem, any instruction fetch or data read from flash by the Cortex-M3 will return invalid data.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory USB/GPIO38: GPIO38/VBUS Cannot be Used as an Output Revision(s) Affected A Details GPIO38 cannot be used as an output and may fail in the system if used as such at any time. Workaround(s) Do not use the output function on this pin. This is fixed in Revision B silicon. Advisory USB: VBUS Pin May Clamp to 3.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory RAM Controller: Cortex-M3 Correctable Error Address Register Always has Value 0x0 Revision(s) Affected 0, A, B Details The Correctable Error Address Register should capture the address for which the correctable error (1-bit ECC error) occurred, but the Correctable Error Address Register mapped to the Cortex-M3 core will always have value 0x0. Workaround(s) None.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory eQEP: eQEP Inputs in GPIO Asynchronous Mode Revision(s) Affected 0, A, B Details If any of the eQEP input pins are configured for GPIO asynchronous input mode via the GPxQSELn registers, the eQEP module may not operate properly. For example, QPOSCNT may not reset or latch properly, and pulses on the input pins may be missed.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory GPIO: GPIO38 and GPIO46 Shunt to VSS Due to Fast Transient Sensitivity at High Temperature Revision(s) Affected 0, A, B Details There is a potential temporary internal shunt to VSS condition identified on pins GPIO38 and GPIO46. In this condition, an on-chip path to VSS is turned on, which can bring down the logic level of these pins below VIL and VOL.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory GPIO: Pins GPIO38 and GPIO46 Cannot be Used for Functions Other Than USB Revision(s) Affected 0 Details Pins GPIO38 and GPIO46 can only be used as USB0VBUS and USB0ID. GPIO and other functions are not available. Workaround(s) None. This is fixed in Revision A silicon.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory FPU: FPU Register Read Following MPYF32, ADDF32, SUBF32, or MACF32 Revision(s) Affected 0, A, B Details This advisory applies when a multi-cycle (2p) FPU instruction is followed by a FPU-toCPU register transfer. If the FPU-to-CPU read instruction source register is the same as the 2p instruction destination, then the read may be of the value of the FPU register before the 2p instruction completes.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory FPU: FPU Register Write Followed by F32TOUI32, FRACF32, UI16TOF32, or F32TOUI32 Revision(s) Affected 0 Details This advisory applies when the execution phase of an FPU register write coincides with the F32TOUI32, FRACF32, UI16TOF32, and F32TOUI32 instructions.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory FPU32 and VCU Back-to-Back Memory Accesses Revision(s) Affected 0 Details This advisory applies when a VCU memory access and an FPU memory access occur back-to-back. There are three cases: Case 1. Back-to-back memory reads: one read performed by a VCU instruction (VMOV32) and one read performed by an FPU32 instruction (MOV32).
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory Control Subsystem I2C: FIFO Interrupt Trigger Levels Capped at 7 Revision(s) Affected 0, A, B Details The TXFFIL (Transmit FIFO Interrupt Level) bits in the I2C Transmit FIFO (I2CFFTX) register and the RXFFIL (Receive FIFO Interrupt Level) bits in the I2C Receive FIFO (I2CFFRX) register are capped to a maximum value of 7. Writes of values greater than 7 to these fields will be truncated to the lower 3 bits.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory Debug: Cross-Trigger Functionality is Limited When Using Breakpoints on the C28x Core Revision(s) Affected 0 Details When cross-triggering is enabled, halting at a breakpoint set for the C28x core does not also halt the Cortex-M3 core. Workaround(s) None. This is fixed in Revision A silicon.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory NMI: Writing a "0" to Any of the CNMIFRC or MNMIFRC Register Bits Clears the Corresponding Flag Bit in CNMIFLG or MNMIFLG Revision(s) Affected 0 Details Writing a "0" to any of the bits in the Control Subsystem CNMIFRC register clears the corresponding bits in the CNMIFLG register.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory Master Subsystem: MNMIFLG.NMIINT Bit Will Not be Set in Some Cases When an NMI is Still Pending Revision(s) Affected 0 Details On the Master Subsystem, if there is a nested NMI and if the user clears the MNMIFLG.NMIINT bit before clearing all the other pending flags while returning from the first NMI handler, then the MNMIFLG.NMIINT bit will not be set while the second NMI is still pending.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory Master Subsystem Boot ROM: NMI Handler Can Return Before Clearing All the Pending NMIs, if There is a Nested NMI Revision(s) Affected 0 Details The Master Subsystem Boot ROM depends on the MNMIFLG.NMIINT bit to determine if there is a pending NMI on the Master Subsystem. However, as mentioned in the advisory titled "Master Subsystem: MNMIFLG.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory C28x Flash: Code Executing From the C28x Subsystem Flash May be Subject to Unnecessary 1-Cycle Delays Revision(s) Affected 0 Details Code executing from the C28x Subsystem Flash may be subject to unnecessary 1-cycle delays. This delay will not occur more often than once every 8 instructions for code that is composed of linear 32-bit opcodes with no pipeline delays (worst case).
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory µDMA: No Transfer Completion Interrupt From SW Channels, Other Than Channel 30 Revision(s) Affected 0 Details On a Concerto device, if any SW channel, other than Channel 30, is used for data transfer, then there will be no completion interrupt generated on the µDMA interrupt line when data transfer is done.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.
Usage Notes and Known Design Exceptions to Functional Specifications www.ti.com Advisory Read of Clock Control Registers on C28x Memory Map is EALLOW-Protected Revision(s) Affected 0 Details Clock Control Registers on the C28x memory map are read-protected by EALLOW. Workaround(s) Enable EALLOW before reading the Clock Control Registers on the C28x memory map. This is fixed in Revision A silicon.
Documentation Support www.ti.com 5 Documentation Support For device-specific data sheets and related documentation, visit the TI web site at: http://www.ti.com.
Revision History 6 www.ti.com Revision History This revision history highlights the technical changes made to the SPRZ357I errata document to make it an SPRZ357J revision. Scope: See the following table. LOCATION Section 4.1.5 Section 4.
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