F28M35H20B1, F28M35H20C1, F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1, F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 Concerto MCU Silicon Errata Literature Number: SPRZ357B August 2011 – Revised January 2012
SPRZ357B – August 2011 – Revised January 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Contents 1 2 3 4 5 6 Introduction ........................................................................................................................ 5 Device and Development Support Tool Nomenclature ............................................................. 5 Device Markings ................................................................................................................. 6 Known Design Marginality/Exceptions to Functional Specifications ..........................................
www.ti.com List of Figures 1 Example of Device Markings .............................................................................................. 6 2 Example of Device Nomenclature ........................................................................................ 6 List of Tables 4 ................................................................... ................................................................................................................
Silicon Errata SPRZ357B – August 2011 – Revised January 2012 F28M35x Concerto MCU Silicon Errata 1 Introduction This document describes the silicon updates to the functional specifications for the F28M35x microcontrollers (MCUs).
Device Markings 3 www.ti.com Device Markings Figure 1 provides an example of the Concerto device markings and defines each of the markings. The device revision can be determined by the symbols marked on the top of the package as shown in Figure 1. Some prototype devices may have markings different from those illustrated. Figure 2 shows an example of the device nomenclature.
Known Design Marginality/Exceptions to Functional Specifications www.ti.com 4 Known Design Marginality/Exceptions to Functional Specifications Table 2. Advisory List Title ...................................................................................................................................... Page Advisory — Debug: Global Run of Cortex™-M3 and TMS320C28x™ is not Operational .....................................
Known Design Marginality/Exceptions to Functional Specifications www.ti.com Advisory Debug: Global Run of Cortex™-M3 and TMS320C28x™ is not Operational Revision(s) Affected 0 Details Due to missing signals in the debug logic, global run of the Cortex™-M3 and C28x™ cores is not enabled. Workaround(s) None. This will be fixed in the next revision of the silicon.
Known Design Marginality/Exceptions to Functional Specifications www.ti.com Advisory NMI: Writing a " 0" to Any of the CNMIFRC/MNMIFRC Register Bits Clears the Corresponding Flag Bit in CNMIFLG/MNMIFLG Revision(s) Affected 0 Details Writing a "0" to any of the bits in the Control Subsystem CNMIFRC register clears the corresponding bits in the CNMIFLG register. Likewise, writing a "0" to any of the bits in the Master Subsystem MNMIFRC register clears the corresponding bits in the MNMIFLG register.
Known Design Marginality/Exceptions to Functional Specifications www.ti.com Advisory Control Subsystem: Reset Value (/8) of CCLKCTL.CLKDIV Bit Field Violates the MIN Requirement Mandated by the Data Manual for ACIBCLK, When the Input Clock to the Divider is Less Than 40 MHz Revision(s) Affected 0 Details On power up or after an external reset (XRS), PLL is bypassed and the Master Boot ROM configures the default SYSCLK divider to "/1". This makes the input clock to the divider the same as OSCCLK.
Known Design Marginality/Exceptions to Functional Specifications www.ti.com Advisory Master Subsystem: MNMIFLG.NMIINT Bit Will Not be Set in Some Cases When an NMI is Still Pending Revision(s) Affected 0 Details On the Master Subsystem, if there is a nested NMI and if the user clears the MNMIFLG.NMIINT bit before clearing all the other pending flags while returning from the first NMI handler, then the MNMIFLG.NMIINT bit will not be set while the second NMI is still pending.
Known Design Marginality/Exceptions to Functional Specifications www.ti.com Advisory Master Subsystem Boot ROM: NMI Handler Can Return Before Clearing All the Pending NMIs, if There is a Nested NMI Revision(s) Affected 0 Details The Master Subsystem Boot ROM depends on the MNMIFLG.NMIINT bit to determine if there is a pending NMI on the Master Subsystem. However, as mentioned in the advisory titled "Master Subsystem: MNMIFLG.
Known Design Marginality/Exceptions to Functional Specifications www.ti.com Advisory GPIO: GPIOs on Port C Do Not Toggle Correctly When Using the GPCTOGGLE Register Revision(s) Affected 0 Details GPIOs on Port C do not toggle correctly when using the GPCTOGGLE register because of a dependency on the state of GPIOs on Port A. Workaround(s) Use GPCSET and GPCCLEAR registers or the GPCDAT register to toggle Port C GPIOs. This will be fixed in the next revision of the silicon.
Known Design Marginality/Exceptions to Functional Specifications www.ti.com Advisory Read of Clock Control Registers on C28x Memory Map is EALLOW-Protected Revision(s) Affected 0 Details Clock Control Registers on the C28x memory map are read-protected by EALLOW. Workaround(s) Enable EALLOW before reading the Clock Control Registers on the C28x memory map.
Known Design Marginality/Exceptions to Functional Specifications www.ti.
Known Design Marginality/Exceptions to Functional Specifications www.ti.com Advisory VREG: VREG 'Warn Lo/High' Feature Does Not Work as Intended Revision(s) Affected 0 Details The VREG "Warn Lo/High" feature should not be used or enabled in the F28M35x Revision 0 devices. Do not set the VREGWARNE bit in the MNMICFG register as it could negatively affect the VREG output voltage. Workaround(s) None. This will be fixed in the next revision of the silicon.
Known Design Marginality/Exceptions to Functional Specifications www.ti.com Advisory RAM Controller: Cortex™-M3 Accesses to Shared RAM (Cx and Sx) and to MSG RAM Do Not Work When Any Other Master (µDMA/C28x/DMA) Simultaneously Accesses the Same Memory Revision(s) Affected 0 Details If Cortex™-M3 accesses Shared RAM (Cx and Sx) or MSG RAM when any other master (µDMA/C28x/DMA) accesses the same memory, data and parity may get corrupted in the memory.
Documentation Support 5 www.ti.com Documentation Support For device-specific data sheets and related documentation, visit the TI web site at: http://www.ti.com. For further information regarding the F28M35x Concerto devices, see the F28M35H20B1, F28M35H20C1, F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1,F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 Concerto Microcontrollers Data Manual (literature number SPRS742).
Revision History www.ti.com 6 Revision History This revision history highlights the technical changes made to the SPRZ357A errata document to make it an SPRZ357B revision. Scope: See table below.
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