Service manual
QD01/QD03/QD41/QD43:AD1855
QL07/QU02:NJU3718
CPIN
CMIN
DOUT
DOUTB
PDDIS
46.08MHz
Phase
comparator
1/2048
divider
1/2
46.08MHz
oscillator
9KHz
9.216KHz
PDO
VI
VO
RESET
OSCON C9M MUTI DAIN
DAOUT
Serial data stream output
MUTO
C1F0
C1F1
C2F0
C2F1
WEB
OEB
DB(7:0)
A (14:0)
SRAM
Address
S/P
Error
correction
SW
DAI
control
Timing
Demoduration
SYNC
Detection-
Safeguard
32K x 8
VCXO
18.432 MHz
LPF
QPSK input
QM09:PM4007A
No. Name I/O Function
51 DB0 B RAM D0
52 VDD - +5VD
53 GND - GND
54 TI1 I TEST
55 VIN I VCXO input
56 VOUT O VCXO output
57 TI2 I TEST
58 TI3 I TEST
59 TLDB I TEST
60 TCK I TEST
61 TRP O TEST
62 TDO O TEST
63 PDO O Phase comparator output (3-state)
64 TI4 I TEST
65 PDDIS I Control input for PDO out At “L” Output ON
66 MUTO O Muting output. Mutes at “H”.
Sets to “H” when MUTI = H or the AC-3 period cnanot be received.
67 TI5 I TEST
68 VLDY O TEST
69 DASYO O TEST
70 DAOUT O Digital OUT (serial data stream output)
71 DAIN I Digital external input : Sets to DAOUT when DASEL is at “H”
72 DASEL I Selects digital OUT
73 TI8 I TEST
74 C2F1 O N.C.
75 C2F0 O N.C.
76 C1F1 O N.C.
77 C1F0 O Displays C1 correction error status. Outputs error count at C1.
78 MUTI I Muting input. Mutes at “H”.
79 VDD - +5VD
80 GND - GND
81 AVDD 1 +5VD
82 CPIN I Analog converter inverted input
83 CMIN I Analog converter inverted input
84 AGND - GND
85 TM4 I TEST
86 VDD - +5VD
87 DIN I TEST
88 DOUT O Analog converter inverted output
89 DOUTB O Analog converter inverted reverse output
90 C9M O N.C.
91 GND - GND
92 WINGT O TEST
93 SYST0 O TEST
94 SYST1 O TEST
95 ADST0 O TEST
96 ADST1 O TEST
97 TM5 I TEST
98 BUNRI I TEST
99 AGND - GND
100
AVDD - +5VD
No. Name I/O Function
1 GND - GND
2 VDD - +5VD
3 RESET I System Reset At “L” reset
4 OSCON I Oscillator control
At”H” during normal operation At “L” during standby
5 DATA I TEST
6 MCK I TEST
7 MLTB I TEST
8 IDST O TEST
9 IDCK O TEST
10 IDO O TEST
11 TM0 I TEST
12 ECCK O TEST
13 DEN O TEST
14 DRY O TEST
15 MSYC O TEST
16 TM1 I TEST
17 A0 O RAM A0
18 A1 O RAM A1
19 A2 O RAM A2
20 A3 O RAM A3
21 A4 O RAM A4
22 A5 O RAM A5
23 TM2 I TEST
24 TM3 I TEST
25 XOUT O TEST
26 XIN I TEST
27 XEXT I TEST
28 GND - GND
29 VDD - +5VD
30 A6 O RAM A6
31 A7 O RAM A7
32 GND - GND
33 VDD - +5VD
34 A12 O RAM A12
35 A14 O RAM A14
36 WEB O RAM WEB
37 A13 O RAM A13
38 A8 O RAM A8
39 A9 O RAM A9
40 GND - GND
41 A11 O RAM A11
42 OEB O RAM OE
43 A10 O RAM A10
44 DB7 B RAM D7
45 DB6 B RAM D6
46 DB5 B RAM D5
47 DB4 B RAM D4
48 DB3 B RAM D3
49 DB2 B RAM D2
50 DB1 B RAM D1
41 42
Pin Input/Output Pin Name Description
1 I DGND Digital Ground.
2 I MCLK Master Clock Input. Connect to an external clock source at either 256, 384
or 512 F
S
.
3 I CLATCH Latch input for control data. This input is rising-edge sensitive.
4 I CCLK Control clock input for control data. Control input data must be valid on the
rising edge of CCLK. CCLK may be continuous or gated.
5 I CDATA Serial control input, MSB first, containing 16 bits of unsigned data per
channel. Used for specifying channel specific attenuation and mute.
6 I 384/256 Selects the master clock mode as either 384 times the intended sample fre-
quency (HI) or 256 times the intended sample frequency (LO). The state of
this input should be hardwired to logic HI or logic LO, or may be changed
while the AD1855 is in power-down/reset. It must not be changed while the
AD1855 is operational.
7 I X2MCLK Selects internal clock doubler (LO) or internal clock = MCLK (HI).
8 O ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has
no signal input for more than 1024 LR Clock Cycles.
9 I DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI.
This is used to impose a 50 ms/15 m
s response characteristic on the output
audio spectrum at an assumed 44.1 kHz sample rate.
10 I
96/48
Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.
11, 15 I AGND Analog Ground.
12 O OUTR+ Right Channel Positive line level analog output.
13 O OUTRÐ Right Channel Negative line level analog output.
14 O FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10
m F and 0.1 mF capacitors to the AGND.
16 O OUTLÐ Left Channel Negative line level analog output.
17 O OUTL+ Left Channel Positive line level analog output.
18 I AVDD Analog Power Supply. Connect to analog +5 V supply.
19 O FILTB Filter Capacitor connection, connect 10 m
F capacitor to AGND.
20 I IDPM1
Input serial data port mode control one. With IDPM0, defines one of four
serial modes.
21 I IDPM0 Input serial data port mode control zero. With IDPM1, defines one of four
serial modes.
22 O ZEROL Left Channel Zero Flag output. This pin goes HI when Left Channel has no
signal input for more than 1024 LR Clock Cycles.
23 I MUTE Mute. Assert HI to mute both stereo analog outputs. Deassert LO for nor-
mal operation.
24 I PD/RST Power-Down/Reset. The AD1855 is placed in a low power consumption
mode when this pin is held LO. The AD1855 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values.
Connect HI for normal operation.
25 I L /RCLK Left/ Right clock input for input data. Must run continuously.
26 I BCLK Bit clock input for input data. Need not run continuously; may be gated or
used in a burst fashion.
27 I SDATA Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of
twos complement data per channel.
28 I DVDD Digital Power Supply Connect to digital +5 V supply.
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD1855
FILTR
OUTRÐ
OUTR+
AGND
96/48
DEEMP
ZEROR
DGND
MCLK
CLATCH
CCLK
X2MCLK
384/256
CDATA
AGND
OUTLÐ
OUTL+
AVDD
FILTB
IDPM1
IDPM0
DVDD
SDATA
BCLK
L/RCLK
ZEROL
MUTE
PD/RST
P9
P10
P11
P12
6
7
8
9
14
P1
DATA
CLK
V
SS
V
DD
STB
CLR
P2
P3
P4
P5
P6
P7
P8
18
12
13
15
16
17
1
2
3
4
10
11
5
CONTROL CIRCUIT
SHIFT REGISTER
LATCH CIRCUIT
NJU3713
19 P1
DATA
CLK
V
SS
VDD
STB
CLR
P2
P3
P4
P5
P6
P19
P20
28
17
18
20
22
23
24
25
26 P7
P8
P9
P10
P11
P12
27
1
P13
P14
P15
P16
5
6
8
9
10 P17
P1811
2
3
4
12
13
SO14
15
16
21
CONTROL CIRCUIT
SHIFT REGISTER
LATCH CIRCUIT
NJU3718
QA51:MC13022
QV01:NJU3713
Q351:LC72720
ATTEN/
MUTE
ATTEN/
MUTE
SERIAL
DATA
INTERFACE
83
INTERPOLATOR
MULTIBIT SIGMA-
DELTA MODULATOR
SERIAL CONTROL
INTERFACE
CLOCK
CIRCUIT
OUTPUT
BUFFER
OUTPUT
BUFFER
DAC
DAC
MULTIBIT SIGMA-
DELTA MODULATOR
VOLTAGE
REFERENCE
VOLUME
MUTE
CONTROL DATA
INPUT
3
2
DIGITAL
SUPPLY
CLOCK
IN
96/48F
S
CLOCK
ANALOG
OUTPUTS
22
ZERO
FLAG
ANALOG
SUPPLY
DE-EMPHASISMUTE
PD/RST
2
SERIAL
MODE
16-/18-/20-/24-BIT
DIGITAL
DATA INPUT
AD1855
83
INTERPOLATOR
3
384/256
X2MCLK