Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 4-7
System Address Map
4.1.2.4 Chipset Specific Range
The address range FE00_0000h - FFBF_FFFFh region is reserved for chipset specific functions.
FE60_0000h - FE6F_FFFFh is used for memory mapped SNC registers. They are accessible only
from the processor bus on that SNC. The E8870 chipset will master abort requests to the remainder
of this region.
4.1.3 High and Low Memory Mapped I/O (MMIO)
Two variable-sized MMIO regions are directed to I/O buses. The Low MMIO region starts at 4 GB
to 32 MB (FDFF_FFFFh), and may extend downward no lower than 64 MB (400_0000h). The
High MMIO region starts below 1 TB (FF_FFFF_FFFFh) and may extend downward in 4-GB
increments no lower than 4 GB (1_0000_0000h). Thus, neither MMIO region overlaps any fixed
regions. No addresses in these regions may have the write-back or write-through cacheability
attribute, but cache flushes to this region are possible. The size of the region is defined by MMIOL
and MMIOH registers in the SNC.
These regions can be divided in half by the SP switches if two SIOHs are present. The MMIOL
register divides the MMIOL region with 64-MB granularity. The MMIOH register divides the
MMIOH region in half with 4-GB granularity.
The subrange assigned to each SIOH can be sub-divided into variable sized spaces for each Hub
Interface. Each Hub Interface can be allocated a multiple of 16 MB (for MMIOL) or 64 MB (for
MMIOH). The subranges allotted to all Hub Interfaces connected to a particular SIOH must be
contiguous. They must also be assigned in this order (highest to lowest) for the SIOH:
HI0,HI1,HI2,HI3,HI4. The subranges allotted to all PCI buses connected to a particular Hub
Interface must be contiguous. The subranges allotted to all PCI buses connected to a particular Hub
Interface device (e.g. P64H2) must be contiguous. This subdivision is controlled by the MMIOBL,
MMIOLL, MMIOBH, and MMIOLH registers in the SIOH.
MMIO also includes the ranges for the Hot-plug controller of the P64H2 and the SAPIC addresses.
Addresses in this range will not be interleaved like memory accesses, but will be directed to one
SPS to enable ordering. For this reason, the SNC routes most addresses in this range to the default
SP.
SNC MMIO Routing Registers in the SNC define the High and Low MMIO ranges. Any
processor request (SNC should not receive SP requests to this range) to
either of these regions is directed out the default scalability port with a
destination of MMIO in the Attr field.
SPS MMIO Routing The SPS routes requests with Attr = MMIO one of two SIOHs. For each
domain, the MMIO range may be directed to one SIOH or the other, or
split between the two. Therefore, each SPS port has a set of registers for
the high and low MMIO ranges (MMIOLS and MMIOHS) that define
boundaries between the subranges routed to each SP port. The MMIOLS
registers are applied if the address is below 4G. Otherwise, MMIOHS
registers are applied.
SIOH MMIO Routing The SIOH has registers that define the MMIO range and the subranges
routed to each Hub Interface. A request from a Hub Interface that falls in
a local Hub Interface subrange is routed there. A Hub Interface request
that falls in the MMIO range, but is not mapped to any Hub Interface in
that SIOH will be sent to a scalability port with Attr = MMIO. The SPS
will route it to the other SIOH. An SP requests that falls in a local Hub