Datasheet

System Address Map
4-8 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
Interface subrange is routed there. An SP request that falls in the MMIO
range, but is not mapped to any Hub Interface in that SIOH will be
master aborted.
4.1.4 Memory Mapped Configuration Space
The entire PCI configuration space is mapped into the MMCFG address range of the SNC. The
processor bus address defines the configuration register to be accessed and the processor bus data
either returns or provides register contents. As opposed to CF8/CFC-based configuration accesses,
this mechanism is atomic. This space is 64 MB in size, must be above 4 GB, and may not overlap
High MMIO. Physical memory that is mapped to this range may not be used or recovered.
Accesses to this range must be 1, 2, 3, or 4 bytes in length. Only UC memory attribute is supported
in this range.
This space is not accessible inbound, only by processors. Inbound accesses to this range will reach
the SNC. If no main memory exists in this space, the SNC will provide a master abort response
status. If (unused) main memory does exist in this space, that memory will be accessed. This access
will not affect other system operations.
If a processor request falls in this range, it may access a configuration register in the SNC or be
converted into a configuration Read/Write to SP. The configuration Read/Write to SP from
MMCFG are routed to an E8870 chipset component configuration register or out a hub interface
like any other configuration Read/Write to SP.
4.1.5 Main Memory Region
4.1.5.1 Application of Coherency Protocol
Table 4-6 defines the conditions under which processor transactions are routed to main memory.
Table 4-8 defines the conditions under which inbound transactions are routed to main memory.
There may be differences in the range C_0000h-F_FFFFh and SMM range. The E8870 chipset
applies the coherency protocol to any accesses to main memory. The E8870 chipset may
malfunction if processors issue.
Software must not set cacheable attributes for these areas. However, processors belonging to the
Itanium processor family may flush a cache prior to making a range non-cacheable, whether it had
ever been cacheable before or not. Therefore, the SNC will drop any BILs to non-coherent space.
Although it is illegal, the E8870 chipset will complete certain coherent operations in the MAR
regions. See Section 4.1.1.4, “C and D Segments” and Section 4.1.1.5, “System BIOS (E and F
Segments).”
The Memory Interleave Range (MIR) registers define the mapping of address space to physical
memory. The MIRs can be programmed to map physical memory contiguously or sparsely. Any
address that is directed with Attr = DRAM that doesn’t map within the MIR region is sent to CB
for a master abort.
4.1.5.2 Routing Memory Requests Initiated on a Processor Bus
When a request appears on the processor bus of a node, and it does not fall in any special region, it
is compared against the MIRs on an SNC. Those registers describe all the memory addressed by
that SNC. If the address is mapped to that node, the request is routed to local memory. If no MIR
matches, the request is directed to the scalability port. Any region of main memory may be mapped
local or remote. In single node systems, all memory is local. In multiple processor bus systems,