Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 4-9
System Address Map
memory is generally global. Multiple processor bus systems use local memory while booting,
however. Local memory can be defined during system operation in multiple processor bus systems,
but this possibility is not validated for E8870 chipset-based systems.
4.1.5.3 Routing Memory Requests Initiated on a Hub Interface
When a request appears on a Hub Interface, and it does not fall in any special region, the request is
directed to the scalability port (SP) with Attr = DRAM. That is, the SIOH routes to SP by
subtractive decode.
4.1.5.3.1 SPS Memory Request Routing
Each port in the scalability port switch (SPS) has a set of MIR registers, which enable different
main memory maps to be defined for each domain. If the destination of a request is DRAM, the
request is compared against the SPS MIRs. The SPS MIRs define the home of each cache line. The
request is directed to the SP specified by the matching MIR. (To minimize decoding time, MIRs
define physical SP numbers rather than node numbers.) If no MIR matches, the SPS will route the
transaction to the node identified by MIR0/Way0.
4.1.5.3.2 Handling Memory Requests at the Home Node
Requests entering the SP to the home SNC are compared against the MIRs to determine local
interleave. The address of a remote request that fails to match a MIR will be captured, and the
illegal address flag will be set in the FERRST register. A response status of master abort is
returned.
4.1.5.3.3 Node Interleaving
Memory covered by each MIR may be interleaved across up to four nodes in two granularities: at
the 128-byte level or at blocks. If the GRAN bit in a MIR specifies 128-byte granularity, bytes 0 to
127 would be located on one node, 128 to 255 on the next node, 256 to 383 on the next, and so on.
If the GRAN bit specifies Block interleaving, the range is divided into four equal-sized blocks,
each of which can be assigned to a different node. For example, 0h to 3FFF_FFFFh of a 4-GB
Memory Interleave range would be located on one node, 4000_0000h to 7FFF_FFFFh on the next
node, and so on.
Both granularities can be used in different ranges at the same time. The 128-byte granularity is
used to distribute memory bandwidth in ranges where a very localized area of memory may
sometimes get very heavy utilization. The Block granularity is used when it is desirable to
associate different ranges with particular nodes (for non-uniform memory access optimizations, or
in systems that support hot add/removal).
4.1.5.3.4 Limitations
• Memory Interleave Range must be a power of two in size and start on a multiple of its size.
That is, a 2-GB range can only start at 2 GB, 4 GB, 8 GB, etc.
• Each SPS MIR defines four nodes that can be interleaved by blocks or at 128-byte granularity.
• Each SNC has eight Memory Interleave Range registers, SPS’s have six MIRs.
• SNC MIRs can define no more than one DDR DIMM row. However, a DDR DIMM row can
be split between multiple MIRs. When this happens, address restrictions apply to the split
interleaves.