Datasheet

System Address Map
4-12 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
To avoid memory scrubbing problems, reflection size must be 4 GB maximum. The highest
address of the reflection is restricted to end on a 4-GB boundary. Both the highest address in the
MIR and the reflection of address FFFF_FFFFh must appear just below a 4-GB boundary
(Nx4GB - 1). This ensures that the address bits A[31:0]# are the same for the reflection of an
address and the original.
The physical memory mapped by MIR1 to 2 to 4 GB can also be mapped to 6 to 8 GB by MIR2.
MIR2/MIT2 is programmed identically to MIR1/MIT1 except for a start address of 6 GB. BIOS
only informs the O/S about the memory in the lower image that is not covered by Firmware or
MMIO, and the remaining physical memory in the upper image. The physical memory “behind”
MMIO and System space in the lower image can be addressed in the upper image. The O/S will not
allocate memory for the regions that are not reported. If an address were (illegally) generated for
the lower portion of MIR2, it would address the same locations as Memory Block1. To improve the
ability of the E8870 chipset to detect illegal addresses, the size of the reflection should be no larger
than required to accommodate MMIOL expansion.
The interleaving used behind MMIOL must be the same as the interleaving in the reflected range.
For example, if the memory behind MMIOL is interleaved across four DIMMs, the same four
DIMMs must be mapped in the reflection. This requires four spare MIRs on whatever SNCs map
those DIMMs.
To avoid memory scrubbing problems, reflections are limited to 4 GB in size. The highest address
of the reflection is restricted to end on a 4-GB boundary. Both the highest address in the MIR and
the reflection of address FFFF_FFFFh must appear just below a four GB boundary.
4.2 Memory Address Disposition
4.2.1 Registers Used for Address Routing
4.2.1.1 SNC Registers
4.2.1.2 SPS Registers
Each SP has a copy of these registers. Addresses that do not hit inside the MIR are sent to the
compatibility bus.
Table 4-2. SNC Memory Mapping Registers
Name Function
MAR[5:0] Defines attributes of individual Compatibility ranges.
Supports shadowing by routing reads and writes to Memory or PCI.
MIR[7:0] Identifies cache lines located on this node.
MMIOL_BAS,MMIOL_LIM Defines the size of the Memory Mapped I/O Region below 4 GB.
MMIOH_BAS,MMIOH_LIM Defines the size of the Memory Mapped I/O Region above 4 GB.
ASE Contains enable bits for VGA, and other ranges and local-firmware.
MMCFG Defines the location of the Memory Mapped Configuration range.