Datasheet

System Address Map
4-14 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
Any other encodings are treated as DND. That is, they are not used for routing. The Attr field is not
used in the routing of coherent requests.
The following tables define the address disposition for the E8870 chipset. Table 4-6 defines the
disposition of outbound requests entering the SNC on the processor bus. Table 4-8 defines the
disposition of inbound requests entering the SIOH on hublinks.
Table 4-6. Address Disposition for Processor
Address Range Conditions SNC Behavior SPS Behavior
DOS 0h to 09_FFFFh Coherent Request to Main
Memory
Route to SNC according to MIR
registers. Apply Coherence Protocol.
VGA/MDA (0A_0000h to 0A_FFFFh or
0B_8000h to 0B_FFFFh) and
VGASE = 0.
Coherent Request to Main
Memory
Route to SNC according to MIR
registers. Apply Coherence Protocol.
0B_0000h to 0B_7FFFh and
VGASE = 0 and MDASE = 0.
(0A_0000h to 0A_FFFFh or
0B_8000h to 0B_FFFFh) and
VGASE = 1.
Issue non-coherent Read/
Write to SP,
Attr = VGA
Route to SIOH node specified by
VGA_PORT register.
0B_0000h to 0B_7FFFh and
MDASE = 0 and VGASE = 1.
0B_0000h to 0B_7FFFh and
MDASE = 1.
MDA:
Issue non-coherent Read/
Write to SP,
Attr = CB
Route to SIOH node in CB_PORT
register.
C and D BIOS
Segments
(See Table 4-1 for
a definition of
MAR encodings)
0C_0000h to 0D_FFFFh and MAR
= 11
Coherent Request to Main
Memory
Route to SNC according to MIR
registers. Apply Coherence Protocol.
Write to
0C_0000h to 0D_FFFFh and MAR
= 10
Read to
0C_0000h to 0DFFFFh and MAR =
01
Read to
0C_0000h to 0D_FFFFh and MAR
= 10
Issue non-coherent Read/
Write to SP,
Attr = CB
Route to SIOH node specified by
CB_PORT register.
Write to
0C_0000h to 0D_FFFFh and MAR
= 01
0C_0000h to 0D_FFFFh and MAR
= 00
E and F BIOS
Segments
(See Table 4-1 for
a Definition of
MAR encodings)
0E_0000h to 0F_FFFFh and
MAR=11 (SNC MARs must be set
to this value.)
Coherent Request to Main
Memory
Route to SNC according to MIR
registers. Apply Coherence Protocol.
Writes to 0E_0000h-0F_FFFFh
and MAR = 10.
Reads to 0E_0000h-0F_FFFFh
and MAR = 01.
Writes to 0E_0000h-0F_FFFFh
and MAR = 01.
If LPC is enabled
a
, set
A[21:20] and issue requests
to LPC,
else,
Issue non-coherent Read/
Write to SP,
Attr = CB
Route any SP request to SIOH node
specified by CB_PORT register.
Reads to 0E_0000h-0F_FFFFh
and MAR = 10.
0E_0000h-0F_FFFFh and
MAR=00