Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 4-15
System Address Map
Low MMIO Above MMIOL.BASE
b
to
FDFF_FFFFh.
Issue non-coherent Read/
Write to SP,
Attr = MMIO
Route to SIOH according to MMIOLS.
E8870 Chipset
Specific
FE00_0000h to FEBF_FFFFh AND
valid SNC memory mapped
register address
Issue configuration access to
memory mapped register
inside SNC.
N/A
FE00_0000h to FEBF_FFFFh AND
NOT a valid SNC memory mapped
register address.
Issue non-coherent Read/
Write to SP,
Attr = CB
(Master Abort)
Route to SIOH node specified by
CB_PORT register.
SAPIC Registers FEC0_0000 to FECF_FFFFh Issue non-coherent Read/
Write to SP,
Attr = MMIO
Route to SIOH according to SARS.
Reserved FED0_0000h to FEDF_FFFFh Writes are dropped without
SP issue.
for reads: Issue non-
coherent Read to SP,
Attr = CB
(Master Abort)
Route PRNCs to SIOH node specified
by CB_PORT register.
Interrupt Interrupt transaction to
FEE0_0000h - FEEF_FFFFh
(not really memory space).
See Table 4-7 See Table 4-7
Memory transaction to
FEE0_0000h to FEEF_FFFFh
Issue non-coherent Read/
Write to SP,
Attr = CB
(Master Abort)
Route to SIOH node specified by
CB_PORT register.
Reserved FEF0_0000h to FEFF_FFFFh Issue non-coherent Read/
Write to SP,
Attr = CB
(Master Abort)
Route to SIOH node specified by
CB_PORT register.
Global Firmware FF00_0000h to FFBF_FFFFh Issue non-coherent Read/
Write to SP,
Attr = CB
Route to SIOH node specified by
CB_PORT register.
Local Firmware FFC0_0000h to FFFF_FFFFh If LPC is enabled, issue LPC
access,
else, Issue non-coherent
Read/Write to SP,
Attr = CB
Route any SP request to SIOH node
specified by CB_PORT register.
High MMIO Enabled MMIOH.BASE
c
to
FF_FFFF_FFFFh
Issue non-coherent Read/
Write to SP,
Attr = MMIO
Route to SIOH according to MMIOHS.
MMCFG 64 MB above enabled
MMCFG.BASE
d
.
Access SNC register, or
issue configuration Read/
Write to SP.
Route like any other configuration
Read/Write.
Main Memory All other Conditions Coherent Request to Main
Memory.
Route to SNC according to MIR
registers. Apply Coherence Protocol.
a. The local firmware hub can be disabled by the LPCEN strapping pin or a bit in the SNC SNCINCO register.
b. See the MMIOL (Low Memory Mapped I/O Space Register) in Section 3.6.4, “MMIOL: Low Memory Mapped I/O Space Register.”
c. See the MMIOH (High Memory Mapped I/O Space Register) in Section 3.6.3, “MMIOH: High Memory Mapped I/O Space Register.”
d. See the MMCFG (Memory Mapped Configuration Space Register) in Section 3.6.6, “MMCFG: Memory Mapped Configuration Space Register.”
Table 4-6. Address Disposition for Processor (Continued)
Address Range Conditions SNC Behavior SPS Behavior