Datasheet

System Address Map
4-18 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
4.2.3 Local/Remote Decoding for Requests to Main Memory
The SNC treats all accesses to main memory as coherent. For main memory accesses, the address
is compared against the local
1
MIR registers to determine whether it accesses local memory or
memory on a different node. Generally, for local accesses, the SP request is just a snoop, and any
memory access is performed by the memory controller. For remote memory accesses, the SP
request will include a read or write to the home node.
Local memory requests are serviced by the SNC memory controller.
4.2.4 Default SP Requirement in Single Node
The default SP port on the SNC and SIOH select which of the two SP ports is used for most I/O
(including memory mapped) and special transactions. It also controls the interleaving between SP
ports for coherent (to main memory) accesses.
For single node systems, the default SP that is programmed into the SNC and the SIOH need to
match. While changing default SPs, there may be a small window where they are different, but
software should make them the same as soon as it can. For example, if the SNCINCO.DefaultSP
was changed to 1, then the default SP in the SIOH (IOCTL.Default_SP) must be changed as soon
as possible after it is known to be a single node configuration. During this window, there should not
be any inbound I/O activity.
4.3 I/O Address Map
4.3.1 Special I/O addresses
Three classes of I/O addresses are specifically decoded by the E8870 chipset:
• I/O addresses used for MDA controllers. These addresses are specifically decoded so they can
be mapped to the CB bus.
• I/O addresses used for VGA controllers. Some of these are also MDA addresses. MDA
remapping takes precedence over VGA remapping.
• I/O addresses used for the PCI Configuration Space Enable (CSE) protocol. The I/O addresses
0CF8h and 0CFCh are specifically decoded as part of the CSE protocol.
The legacy 64 KB I/O space actually was 64 KB+3 bytes. For the extra 3 bytes, A[16]# is asserted.
The E8870 chipset decodes only A[15:3]# when the request encoding indicates an I/O cycle.
Therefore, accesses with A[16]# asserted are decoded as if they were accesses to address 0 and
have been forwarded to the compatibility bus. The full address is sent to the SIOH and the P64H2
or ICH4.
At power-on, all I/O accesses are mapped to the compatibility bus.
1. The SNCs MIRs define local interleave ranges. The SPS’s MIRs define global interleave ranges.