Datasheet

System Address Map
4-20 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
starting at 53BCh includes 53BC-53BFh. Since A[9:0] = 3BFh for 53BFh, it should be routed
to CB.
2. I/O Addresses Used for VGA Controllers:
If the VGASE bit in the ASE register is set, and each addressed byte is in the following range
(A[15:10] are ignored for this decode): A[9:0] = 3B0h-3BBh, 3C0h-3DFh, an I/O Read/Write
will be sent out the default SP with Attr=VGA. For example, a 2-byte read starting at 23BBh
includes 23BB-23BCh. Since A[9:0] = 3BCh (not one of the VGA bytes), the access is not
routed to VGA.
3. Configuration Accesses:
If a request is a DW accesses to 0CF8h (see CFGDAT register) and 1 to 4B accesses to 0CFCh
with configuration space is enabled (see bit 31 of CFGADR register), the request is considered
a configuration access. If the device and bus match the SNC, it will cause an internal
configuration access. If not, a configuration Read/Write is sent to the SP.
4. ISA Aliases:
If the ASE.ISAEN is set, addresses X100h-X3FFh, X500h-X7FFh, X900h-XBFFh, and
XD00h-XFFFh will result in a I/O Read/Write sent out the default SP with Attr = CB.
5. Redirection to Compatibility:
The SNC IORD register enables any 4KB aligned pair of 2KB segments of the I/O space to be
redirected to the compatibility bus. The SNC will issue I/O Read/Write with Attr = CB.
6. Otherwise, an I/O Read/Write is sent to the SPS with Attr = DND.
The SPS will:
• Send I/O Read/Writes with a Attr of VGA to the port as determined by VGA_PORT.
• Send I/O Read/Writes with a Attr of CB to the port as determined by CB_PORT.
• Send I/O Read/Writes accesses to the correct port according to IOPORTS and SIOH_MAP
registers.
The SIOH will forward accesses as follows:
• I/O Read/Writes with Attr = VGA are sent to the VGA link defined in the IOCTL register. If
no VGA link is defined, the SIOH master aborts.
• I/O Read/Writes with Attr = CB are sent to the compatibility bus link. If the CB enable is not
set in the IOCTL register, SIOH master aborts.
• I/O Read/Writes with Attr = DND are sent to the link defined by the IOL register. The IOL
register must be configured to route addresses less than 1000h to the compatibility bus. If the
request falls outside the I/O range defined by the IOL, the SIOH master aborts.
4.3.3 Inbound I/Os
Inbound I/Os are not supported. The E8870 chipset does not support peer-to-peer reads or writes to
I/O space. Any Inbound I/O access that makes it to Hub Interface will receive a master abort
response.
4.4 Configuration Space
The P64H2 and ICH4 will not accept PCI Configuration Cycles. The SIOH will master abort any
configuration cycles on Hub Interface.