Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 4-21
System Address Map
The E8870 chipset provides memory mapped configuration mechanisms. See Section 4.1.4,
“Memory Mapped Configuration Space” and Section 4.1.2.4, “Chipset Specific Range.”
4.5 Illegal Addresses
4.5.1 Master Abort
The term “master abort” is used in E8870 chipset specifications as shorthand for “Reads return all
1’s. Writes have no effect.” The SNC will master abort processor transactions by one of the
following methods:
• Re-directing them to the compatibility bus. That is, a non-configuration Read/Write will be
routed out an SP with the Attr field set to “CB”.
• Dropping writes without SP issue or memory update.
• Dropping 0 length transactions.
When the SNC must master abort a SP request, it sets the response status bits to “master abort.”
When the SNC receives a master abort response status to a read request, it must provide all 1’s data
on the processor bus. When a write returns a master abort response, the write is completed as usual.
4.5.2 Processor Requests
If the SNC has no memory mapped to this address in systems without an SPS (Address matches no
MIR when SPBS bit in CBC register is set), memory writes and IWBs will be dropped without SP
issue or memory access. Memory reads with clean snoop response will return all 1’s. The Illegal
Outbound Address bit will be set in the FERRST or SERRST register.
4.5.3 Scalability Port Requests
The SNC will check the address of any SP requests that may require a memory access against the
MIRs. If the SP request falls outside the memory supported on that SNC, no memory access or
processor bus request will be issued. If the request is a speculative memory read, it will be dropped.
Any SP request that requires a response will set the response status to master abort.
A configuration Read/Write whose bus number and device ID do not match CBC.BusID and
CBC.NodeID respectively will not cause a configuration access. It will receive the usual response
with response status = master abort.