Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 5-1
Memory Subsystem 5
The memory subsystem consists of:
• Memory controller and data buffers
• DDR-SDRAM memory hub interface component (DMH) and DDR DIMMs
The memory subsystem architecture requires that all memory control reside in the SNC, including
memory request initiation, refresh, configuration access and power management.
The timing of all accesses is completely controlled by the SNC.
The memory controller will re-order accesses to minimize bubbles due to page replacement and
read/write transitions. Reads may pass writes. Read data to the same address as a pending write
will be supplied from SNC data buffers; so that the write need not be flushed to memory before
issuing the read.
5.1 Memory Controller Operation
5.1.1 Memory Arbitration
Only in rare cases does arbiter bandwidth limit performance. The memory decoder can accept one
request each cycle. This rate may fall behind memory issue in some circumstances since processor
requests to remote memory must be discarded. For balanced loads in a four-node system, 75% of
local requests may be remote. For the Itanium 2 processor, one request can be forwarded every four
cycle. Memory requests can be handled by the copy engine when a read hits a posted writes, but
can only dispatch one request every eight cycles.
The memory controller accepts requests from the processor bus, Remote Memory Request Queue
and Local Memory Request Queue. Processor requests are granted priority access to the decoder so
that processor request service is simplified by having a fixed pipeline. The processor request does
not take up more than 1/3 of the decoder bandwidth because of their limited issue rates. Whenever
a processor request is not present, remote and local requests are granted in a round-robin fashion.
Table 5-1. General Memory Characteristics
Item Description
DRAM Types DDR-SDRAM
Memory Modules 72-bit DDR-SDRAM DIMMs
DRAM Technologies 128, 256, 512 Mb and 1 Gb
a
densities
a. 1Gb devices are not validated at the time of writing.
Speed Grades DDR: Tcas = 1.5, 2.0, 2.5. Trcd = 20, 30, 40 ns
Peak Bandwidth 6.4 GB/s
Interface Four main channels operated in parallel
Maximum Memory 128 GB (1 Gb DDR-SDRAM)
Minimum Memory 512 MB (128 Mb DDR-SDRAM)