Datasheet

Memory Subsystem
5-2 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
5.1.2 Reads
5.1.2.1 Read Decoding
The request is decoded for interleave range, then for targeted memory resources (channel, device/
DIMM row, DRAM row, DRAM column) and destination. If a read does not fall in a range covered
by the SNC MIRs (a “MIR miss”, see Section 3.6.9, “MIR[9:0]: Memory Interleave Range
Registers”), the memory controller will drop the request. A MIR miss on a processor request means
the addressed memory is in another SNC, or the access was a programming error. SP initiated MIR
misses can only occur due to mis-configuration or address corruption.
5.1.2.2 Read to Same Line as a Posted Write
In parallel with the decode, the read address is compared against the posted writes waiting in the
write request buffer. If there is a match, the data in the buffer allocated to the most recent write,
which is copied to the data buffer allocated to the read.
5.1.2.3 Read Issue in the Idle Case
If the read is not to the same address as a posted write, and no older enqueued to be issued, the
memory read is issued without conflict check to the memory array.
5.1.2.4 Read Cancellation
The memory controller performs speculative reads for any processor read request that decodes to
local memory or whenever a speculative memory read is received on the SP. If they have not
advanced beyond the arbitration stage where they are committed to issue, they may be canceled.
This happens if the processor request receives an implicit write-back response or a speculative
memory read cancel request on the SP. It can also happen whenever a coherency conflict is
detected, or a processor transaction is retried. In the idle case, a cancellation is rarely in time to
prevent issue, but under load, when reads accumulate in the re-order buffers, the cancellation can
save memory bandwidth. If a cancel is issued too late, the returned data will not be used.
5.1.2.5 Read Queueing
There is a 31 entry read queue and four two-entry re-order queues. When there are 27 reads in the
read queue, BPRI# will be asserted and the remote memory queue will not be popped until the level
of the queue drops to 20.
5.1.2.6 Read Re-Ordering
The SNC always issues the critical main channel packet (MCP) first. That is, the addressed byte
always appears in the first of the two MCP packets issued to satisfy a processor memory read.
If an older read is ready to issue, or the required memory resources are busy, the read will be sorted
into one of four re-ordering queues. The reads are sorted so that all accesses with timing
dependencies on each other will appear in the same queue. The reads at the head of the re-ordering
queues are checked in round-robin order for resource conflicts against outstanding accesses.
Requests with timing conflicts are not selected for issue.
Table 5-2 defines how the queues are indexed. The least significant index is the channel bit if the
cache line interleave in the range of interest may cross channels. If the interleave stays on one
DIMM, the least significant index is Bank[1].