Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 5-3
Memory Subsystem
5.1.3 Writes
5.1.3.1 Write Decoding
Writes are decoded for interleave range, then for targeted memory resources (channel, device/
SDRAM row, DRAM row, DRAM column) and destination. If the write is not in any range
described by the MIRs on that SNC (a “MIR miss”, see Section 3.6.9, “MIR[9:0]: Memory
Interleave Range Registers”), the memory controller will drop the request. The scalability port
protocol cluster is informed of processor initiated MIR misses (must be a remote access or
addressing error), so that it will request data from the other node. The scalability port protocol
cluster has a dedicated copy of the MIR decoder to verify that an SP initiated write hits memory
supported by that SNC. Otherwise, the Illegal Address bit in the FERRST register is set.
If no reads are ready to be issued, the memory resources accessed by the new request are compared
against the resources used by outstanding transactions. If no timing conflict exists, and data is
ready in the data buffer, the write request is eligible for issue to the memory array.
5.1.3.2 Write Posting Queue
If the write is not immediately issued, it is stored in a Write Posting Buffer. This buffer can hold 64
writes. If there are 60 writes in this buffer, BNR# will be asserted, and SNC will stop accepting
requests. All but three posted writes are guaranteed to complete as long as the memory controller
stops accepting reads (see Section 5.1.3.3, “Write Re-Ordering”). When the number of writes drops
below 56, BNR# will be deasserted and the SNC will start accepting writes again.
Once SNC posts a write, it guarantees that data is provided to subsequent reads, as if the write to
memory had already taken place.
Reads to the same address as a posted write are handled as described in Section 5.1.2.2, “Read to
Same Line as a Posted Write.”
5.1.3.3 Write Re-Ordering
Writes are selected from the posted write buffer in FIFO order and stored in one of four re-ordering
queues. The writes at the head of the re-ordering queues are checked in round-robin order for
resource conflicts against outstanding accesses. Since the writes in different queues are guaranteed
to access independent resources, selecting them from queues in round-robin order reduces
conflicts. Table 5-2 defines how the queues are indexed.
5.1.3.4 Write Flushing
The Minimum Write Burst Length bit in the Memory Control register (MC.MWBL) controls a
write bursting optimization. If this bit is not set, writes are not required to meet a quota before
being issued. They will be issued to the memory as long as no reads are issued.
Table 5-2. Indices to Re-Ordering Queues
Index
DDR
All Cases
1 Bank[0] is selected.
0 If all bits of MIR.WAY are set, Bank[1] is selected; If not, Channel[0] is selected.