Datasheet

Memory Subsystem
5-4 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
If this bit is set, the SNC will accumulate writes before bursting them:
• Whenever no reads are ready to be issued, and a sufficient interval has elapsed since the last
read to allow a write to be issued immediately, and there are four writes to flush, at least four
writes will be issued. This burst will continue until all writes are completed or a read is
accepted by the memory controller. According to this policy, up to three writes can be posted
indefinitely in the SNC.
MC.MWBL can be cleared to flush writes in the SNC.
Each DMH can hold up to eight writes. In order to flush all these writes to memory, software must
issue eight writes to different cache lines. Ideally these will be full-line writes, because partials will
cause a read-modify-write sequence in memory that may be undesirable. Writes to different lines
will avoid processor bus retries and write combining of partials in the SNC.
5.1.3.5 Partial Writes
The SNC is optimized for cache line writes and reads. For write operations of less than a cache line
in size, the SNC will perform a read-modify-write cycle in the DRAM, by merging the write data
with the previously read data. The SNC only handles one partial write at a time. The SNC does not
post partial writes until the merge is complete. During the merge, any processor access to the same
line as a partial write will be retried.
5.2 Error Correction
To correct errors in memory, the memory controller will “walk” the MIR registers, reading, then
writing each location. When an error is detected, the memory controller will log the address and
syndrome, signal a correctable error on the error pins, and write back the corrected or poisoned (for
non-correctable) value to memory. A non-correctable memory error uncovered by the scrub engine
is not a fatal error.
Scrubbing will be disabled by default. To enable this function, the Scrub Enable bit in the MTS
register (see Section 3.7.7, “MTS: Memory Test and Scrub Register”) must be set.
5.2.1 Scrub Address Generation
One location is scrubbed every 64-K cycles. The scrub engine starts with MIR[0].Base and scrubs
each address defined by MIR[0].Ways until it reaches the highest address in the Interleave Range
specified by MIR[0].Base and MIR[0].Size. Then it scrubs the addresses covered by MIR[1] and so
on, until all the addresses defined by all the MIR registers are scrubbed. Disabled MIRs
(Ways=0000) are skipped. When all MIRs are scrubbed, it starts over with MIR[0].
The SNC must perform the scrub read-modify-write atomically. That is, they must be enqueued
back-to-back to ensure that no system write is ordered between them. If this happens, the scrub
may overwrite a system write. To detect such a conflict, addresses of scrub writes are compared
against processor writes. The processor bus addresses are compared rather than the decoded
memory address (row, column, bank).
When reflection is used to recover memory “behind” the range from the bottom of MMIOL to
4 GB, multiple MIRs can describe different addresses that select the same physical memory
location. Section 4.1.5.4, “Recovering Main Memory Behind Other Regions: Reflections”
describes this technique.