Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 5-5
Memory Subsystem
The operating system guarantees that only one of these addresses will be generated by a processor.
No conflict will be detected between a processor write to the legitimate address and a scrub write to
the alias. Therefore, the scrub engine must not generate writes to the aliases. Use of reflections are
limited to recovering memory behind MMIOL to allow scrub hardware to identify these aliases.
Then there are only two cases of aliases, addresses in the range MMIOL.BASE - 4 GB, and the
complementary range in any MIRs used for the upper reflection. To avoid these aliases, the scrub
engine will not generate writes to these two address ranges:
(A[43:32] = 000h) AND (FFh >= A[31:24] > MMIOL.BASE)
MIT.RFLCT AND (A[31:24] <= MMIOL.BASE)
The MIT.RFLCT bit will be set for any MIR used for MMIOL reflection. The top of the reflection
is restricted to end on a 4-GB boundary so to eliminate addresses in the reflected range which may
or may not be aliases. The reflection of the range from MMIOL.BASE to 4 GB is scrubbed, but no
other addresses in the reflected MIR.
5.2.2 Correction for System Accesses
Correctable errors found in normal read traffic will be corrected and forwarded to the processor bus
or SP, but not written back to memory. Any error remains in memory until they are scrubbed. One
data buffer will be reserved for the scrub engine, so that it does not need to perform data buffer
allocation.
Data from memory normally does not flow through correction logic. If the SNC encounters an
error, data flow will switch to a “correction pipe” with longer latencies. The SNC will continue to
deliver data with a longer latency until a break in traffic allows data flow to be returned to the
normal pipe.
5.2.3 Software Scrubs
Since read errors are not corrected immediately, one memory error may result in frequent
correctable error interrupts. To reduce the possibility of a second failure producing an un-
correctable error, and to avoid performance loss until the scrub engine reaches the error, software
scrub is recommended.
5.2.4 Memory Error Correction Code
The code layout is illustrated in Figure 5-1 and Figure 5-2. Each packet on the four SNC main
channels is split into two codewords. The first codeword appears in transfers 0-3, and the second in
transfers 4-7. The codeword spans the four SNC main channels, consisting of 32-bytes of data
covered by 32 checkbits. An SNC fetch of 128-bytes will be four codewords.
The figures show the position of each data bit (D[255:0]) of the 32-bytes of data and the 32
checkbits (C[31:0]) in each codeword. The least significant 32-bytes of the 64-byte access is
transferred first.
Each code word consists of 32 symbols, eight on each of the four main channels. The division of
bits into symbols is the same on each channel, but checkbits are assigned to different symbols on
different channels. On each main channel, symbols a, b, c, d, e, and f are 8-bit symbols, while g and
h are 12-bit. One symbol in each codeword can be corrected. Errors in more than one symbol are
not correctable. More than 99.9999% of errors confined to two symbols are guaranteed detected.