Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 5-9
Memory Subsystem
All addresses mapped by the MIR will be tested whether they fall in ranges mapped to main
memory or not. For example, addresses will still be tested where the MIR overlaps MMIOL.
Prior to test, the first 32 lines in the MIR must be written with a test pattern. Setting the MTS
MTS.GO bit causes the test pattern to be duplicated throughout the range.
The memory controller must be able to service processor requests to addresses outside the test
range while memory test is running. When the operation is complete, the go bit is reset. After the
go bit is reset, the data at the end of the range can be inspected. If the data values at the end of the
range match the values at the beginning of the range before the test, then all locations in the range
have been written to the correct values and read out (only the data values for enabled ways should
be examined). If the data values do not match, all cache lines above the fault should be corrupted.
Binary search of the range will quickly isolate the faulty address. Multiple patterns must be run to
stress memory fault mechanisms.
5.3 DDR Organization
DDR organization is shown in Figure 5-3. Up to four DIMMs can be placed on each of the two
DDR channels supported by the DMH. Exactly one DMH is placed on each main channel.
5.3.1 DDR Configuration Rules
5.3.1.1 Permissible Configurations
•
Exactly one DMH on each main channel.
• The DIMMs off each DMH must be symmetrical with the DIMMs off all the other DMHs.
Therefore, each slot must hold the same type of DIMM on DMH 0, 1, 2, and 3. The memory
upgrade granularity is the row of four DIMMs, one on each DMH, which collectively provide
a cache line.
• 1, 2, 3, or 4 DIMMs of different types can be placed on each DMH DDR channel.
• The two DDR channels on a DMH need not have the same number or type of DIMMs.
• Electrical considerations restrict DIMM placement to be contiguous starting with the furthest
slot. Only these configurations will be validated.
• Up to eight different DIMM technologies (banks, rows, columns) are supported. Thus each of
the eight possible DIMM rows can be different technologies.