Datasheet

Memory Subsystem
5-10 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
5.3.1.2 Configuration for Performance
For best performance, the amount of memory on each DMH DDR channel should be the same.
5.3.2 DDR Features Supported
5.3.2.1 Write Posting in the DMH
Writes will be posted in the DMH to eliminate the bubble produced when writes must be delayed
until read data returns from the DIMMs. When the SNC issues a write, the data from the previous
write is sent. This allows write data to be issued on the main channel with the same delay between
column command and data as reads.
The DMH can post 512 bytes of data, so it posts four 128-byte writes when connected to the SNC.
Writes are posted in an four-deep FIFO queue in the DMH.
Figure 5-3. Typical DDR-SDRAM Memory System
SNC
Processor Bus
DMH
DDR DIMMs DDR DIMMs
DMH
DDR DIMMs DDR DIMMs
DMH
DDR DIMMs DDR DIMMs
DMH
DDR DIMMs DDR DIMMs
RD[17:0]
RD[35:18]
RD[53:36]
RD[71:54]
Table 5-3. DDR-SDRAM Total Memory Per SNC
DIMM size
Total Number of DIMMs in the Memory System
4 8 16 32
16M x 72 512 MB 1 GB 2 GB 4 GB
32M x 72 1 GB 2 GB 4 GB 8 GB
64M x 72 2 GB 4 GB 8 GB 16 GB
128M x 72 4 GB 8 GB 16 GB 32 GB
256M x 72 8 GB 16 GB 32 GB 64 GB
512M x 72 16 GB 32 GB 64 GB 128 GB