Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 5-11
Memory Subsystem
The DMH will compare read addresses to the posted writes and substitute queued data for DIMM
data with the same timing as a DIMM read. The SNC delays read and write issue on the main
channels to avoid timing conflicts on the DDR data bus and in the DRAMs. Since the write issued
on main channel causes a write to a different address on the DDR bus, the SNC must use the DDR
address for timing conflict checks.
5.3.2.2 DDR Reordering Policies
See Section 5.1.2.6, “Read Re-Ordering”and Section 5.1.3.3, “Write Re-Ordering” for a discussion
of SNC re-ordering in general. DDR timing conflict detection for purposes of re-ordering are
handled as follows:
The SNC will store the channel, device (DIMM side) and bank of the four most recent reads,
writes, or refreshes in four Busy Bank registers. It will issue no requests to the same channel,
device and bank as a valid Busy Bank registers. A request in a Busy Bank registers is invalidated:
• Eight cycles after the decision to issue the request.
• When changing from read issue to write issue. The timing must be such that reads in the Busy
Bank registers never delay write issue and vice-versa.
As the DMH invariably issues column commands with auto-precharge, the bank is always closed
after access. Therefore, the SNC will not issue page hits back to back or give page hits any priority
above requests in the other three queues as it does in RDRAM mode. A page hit will conflict with
any requests still in the Busy Bank registers and will not be issued until they are invalidated.
Requests to the same channel, but different DIMM side (device) will not be issued until the DIMM
data turnaround timing conflict is cleared. For 64-byte accesses, the last request comparison only
prevents issue in the slot (RAMBUS packet) after the last request. For 128-byte accesses, the last
request comparison prevents issue in the two slots following the last request.
5.3.2.3 Refresh
Regardless of the number of DIMMs installed, the SNC will issue 16 refreshes every 15.6 us. The
16 refresh cycle through all eight DIMM sides and both channels. This will not be synchronized to
the RAMBUS maintenance operations.
5.3.2.4 Access Size
The SNC memory read and write commands (MCPs) on main channel perform 128-byte transfers.
The four DMHs that provide each transfer must be configured to transfer 32-bytes when connected.
When in 32-byte mode, the DMH transfers two main channel data packets for each request. The
SNC sets MCP address so that the critical 64-bytes is transferred first.
5.3.2.5 DDR Address Bit Mapping
Each DIMM on an SNC will be assigned a Memory Interleave register. The address bit mapping
can be different for each DIMM. DIMMs of the same or different technology may be interleaved.
When eight DIMMs are populated, all MIRs will be used. This means that each DIMM can only be
interleaved one way.
Within each interleave, address bits are mapped to the channel, device, row, column, and bank bits
in different ways depending on the number of DIMM sides in the interleave. For details, see the
description of the MIR and MIT registers. The mapping scheme is arranged to minimize the delay
associated with address bit mapping.