Datasheet

Intel

E8870 Scalable Node Controller (SNC) Datasheet 1-3

Introduction

1.3 Architectural Overview

Figure 1-2 is a conceptual depiction of the SNC’s queueing structures. The system bus logic

includes the In Order Queue (IOQ) that tracks pipelined in order transactions.

The local access transaction tracker (LATT) is a buffer that holds processor requests until they are

completed. The LATT then converts processor requests into scalability port (SP) requests, which it

inserts into the SP Request Out Queue for SP0 or SP1. The response returns in the SP Response In

Queue on the same SP. The LATT picks a request from one SP or the other, and sends it to the

processor system bus interface. See Section 1.4.3 for more information on SP queues.

The remote access transaction tracker (RATT) pulls SP requests from the SP Request In Queue

from one SP or the other. The request is stored in the RATT until completed.

Requests entering the SNC are presented to Conflict Resolution logic one at a time to resolve

coherency races. If a request is to the same address as a request already stored in the LATT or

RATT, Conflict Resolution logic blocks progress of one request or another until ordering is

resolved.

Memory writes from the various sources are posted in the Write Post Queue, and reads into the

Read Re-ordering Queue. From there, the memory controller selects them for issue to maximize

memory performance. See Chapter 5, “Memory Subsystem” for more information on the queueing

structures in the memory controller.

All data passes through the data buffer when it moves between the processor system bus, memory

and the SPs. The LATT provides configuration register access for processors, and the RATT

provides access from the SP port.

Figure 1-2. Scalable Node Controller Queueing Structures

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RAC Channel

Memory

Controller

System Bus Interface

SP0

LATT and RATT

Queueing Structures

Data

Buffer

SP1