Datasheet

Memory Subsystem
5-12 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
The minimum configuration is 512 MB: 1 DIMM (total of 128MB) device on each DMH. The
maximum configuration is 128 GB: 8 DIMMs (total of 32GB) devices on each DMH.
Fixed Field
Table 5-5 shows address bit mapping for various DDR technologies. In order to minimize address
mapping hardware, as many address bits as possible are directly mapped to row and column bits in
the Fixed field. Note that CA[7,8] and RA[9] do not appear in the Fixed field as they must appear
in the interleave field for some cases.
Since the size of the minimum SNC memory access is 64-bytes (one packet on each main channel),
address bits below A[6] are not mapped to the main channel packet. SNC always sets CA[0] = 0.
Conceivably, the main channel packet could be split into a early and late half, and the DMH could
Table 5-4. Bits Used in MCP Packet for Different DDR Technologies
Technology Organization Row Bits Column Lines Bank Lines
128 Mb
16M x 8 RA11-RA0 CA9-CA0 B1-B0
32M x 4 RA11-RA0 CA11, CA9-CA0 B1-B0
256 Mb
32M x 8 RA12-RA0 CA9-CA0 B1-B0
64M x 4 RA12-RA0 CA11, CA9-CA0 B1-B0
512 Mb
64M x 8 RA12-RA0 CA11, CA9-CA0 B1-B0
128M x 4 RA12-RA0 CA12,CA11, CA9-CA0 B1-B0
1 Gb
a
a. 1Gb devices are not validated at the time of writing.
128M x 8 RA13-RA0 CA11, CA9-CA0 B1-B0
256M x 4 RA13-RA0 CA12, CA11, CA9-CA0 B1-B0
Table 5-5. DDR Address Bit Mapping
Field Address Line Row Column or Bank Bits
High-Order Field 43:26
Any bits required by technology, but not in interleave field are
assigned to address bits in this order (lsb first):
CA[7],CA[8],CA[9],CA[11],CA[12],
RA[9],RA[10],RA[11],RA[12],RA[13]
Fixed Field
25 RA[8]
24 RA[7]
23 RA[6]
22 RA[5]
21 RA[4]
20 RA[3]
19 RA[2]
18 RA[1]
17 RA[0]
16 CA[2]
15 CA[3]
14 CA[4]
13 CA[5]
12 CA[6]
Interleave Field 11:6 See Table 5-6.