Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 5-13
Memory Subsystem
provide the critical word in the early half of the main channel data packet. However, the SNC does
not perform this optimization. All main channel data packets have the same data bit mapping. The
SNC always sets CA[10] to indicate auto-precharge, and it is never mapped to any address bit.
Interleave Field
Table 5-6 shows how low-order address bits are mapped to any DDR Channels, DIMM sides and
DRAM Banks that are included in an interleave. In some cases, there are not enough of these
resources to fill the interleave range, in which case Column [7:8] or Row [9] are used to fill in.
Column[1] is mapped to A[6] for 128-byte lines so that the second 64-byte access hits the same
page as the first.
The maximum DDR configuration has eight DIMMs. Therefore, each DIMM can be assigned one
of the eight MIR/MIT register pairs. The ways field of the MIR registers can be used to include
multiple DIMMs in an interleave. This is indicated by the “MIR” entries in the tables below.
Entries marked MIR indicate that these bits are used to match the ways field of a MIR register.
One MIR entry in a column imply a two-way interleave across a pair of MIRs. Optimally, the
DIMMs described by the two MIR/MITs should be on different channels.
Two MIR entries in a column imply an interleave across four MIRs. Optimally, the MIRs selected
by the least significant address bit should describe different channels. The four-way interleave
increases the probability of data turnarounds, but reduces the probability of page replacements. The
net result is improved performance. The other MIRs in an interleave may or may not describe a
different technology.
Accesses to different DDR channels and banks within the same device will not have timing
dependencies. Accesses to different DIMM sides on the same channel will have to wait for a bus
turnaround. Accesses to different column bits in the same bank will have to wait for a precharge.
Notice the pattern irregularity in the Single-Sided 4/4 column. B0 and CA7 are swapped to avoid a
page replace bubble in a linear access sequence for 64B lines.
A [7:8] is used to define the ways of the Memory Interleave Ranges. Read-Reorder Queue index
[1] is set to Bank[0]. Index[0] is set to Bank[1] for 4/4 ways or Channel[0] for 1/4 and 2/4 ways.
Optimal configurations will map A[7] to Channel[0] by having the MIRs selected by A[7] = 0
control one channel, and MIRs selected by A[7] = 1 controlling the other channel.
Table 5-6. Interleave Field Mapping for DDR
Address Bank (B), Device (D), Channel (Ch), Column (C)
Line Length Single-Sided Double-Sided
128B 64B
# Ways # Ways
1/4 2/4 4/4 1/4 2/4 4/4
A[11] A[10] CA[7] CA[8] CA[9] D[0] CA[7] CA[8]
A[10] A[9] B[0] CA[7] CA[8] B[0] D[0] CA[7]
A[9] A[6] B[1] B[0] B[0] B[1] B[0] D[0]
A[8] A[8] MIR B[1] CA[7] MIR B[1] B[0]
A[7] A[7] MIR MIR B[1 MIR MIR B[1]
A[6] A[11] CA[1] CA[1] CA[1] CA[1] CA[1] CA[1]