Datasheet

Memory Subsystem
5-14 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
High-order Field
Bits that are required to address a given technology (the number of rows, columns or channels
specified by the MIT register), but do not appear in the fixed or interleave fields, appear in the
high-order range. These bits are assigned to address bits as defined in Table 5-5.
Note: CA[10] does not appear in this field, since DDR uses this for an auto-precharge indication.
No bit in the high-order field is mapped to an address bit under all conditions. RA[10] and RA[11]
are used for all technologies, but may be forced to 1 or 0 for DIMM splitting described rather than
being assigned to an address bit (see “DIMM Splitting” ).
RA[12] and RA[13] only exist for larger technologies. They may also be forced for DIMM
splitting. CA[7] and CA[8] exist for all technologies, but may be used in the interleave field.
CA[10], CA[11], and CA[12] only exist for larger technologies.
DIMM Splitting
In order to interleave larger DIMMs with smaller, it is necessary to “split” the larger DIMM into
smaller portions. For each memory location to have a unique address, the most significant row bits
of each portion must be assigned mutually exclusive values. This can be done by restricting the
address ranges (using MIR.BASE) to which the portions are assigned, but this complicates
memory mapping software. The MIT.DIV and MIT.RAFIX fields have been introduced to allow
each portion to be assigned arbitrary address ranges.
MIT.DIV defines whether a DIMM is whole or split into halves or quarters. MIT.RAFIX assigns
1 or 0 values to the necessary number of most significant row bits. Then the different portions can
be assigned arbitrary address ranges (MIR.BASE) (see Table 5-7).
5.3.3 Power Management
DIMMs can be powered down by programming DMH registers using the DMH register write
command in the SCC register.
Clock control will not be provided by the DMH to the DDR DIMMs. The major factor contributing
to DDR power dissipation is the access rate and the data patterns associated with the requests. The
SNC will not determine if the access rate and associated data patterns are high enough to pose a
danger to DDR devices. The SNC will not monitor the temperature of DDR devices. The SNC will
not provide a mechanism to throttle traffic if another agent detects an over temperature among the
SDRAMs. It will be the responsibility of the system designers to ensure enough air flow and
ambient temperature to guarantee that maximum device temperatures are not exceeded.
Table 5-7. MCP Bits Forced by RAFIX and DIV Fields for DIMM Splitting
NUMROW
012
If DIMM is split (MIT.DIV[1]=1) then RAFIX[1] is assigned to: RA[11] RA[12] RA[13]
If DIMM is split in four (MIT.DIV[0]=1) then RAFIX[0] is assigned to: RA[10] RA[11] RA[12]