Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 5-15
Memory Subsystem
5.3.4 DDR Maintenance Operations
The maintenance operations that may occur are DIMM Refresh, DMH Current Calibration, DMH
Temperature Calibration, SNC RAC Temperature Calibration, and SNC RAC Current Calibration.
The current and temperature calibration period (100 ms) is long enough that there is not a
significant performance impact.
DDR refreshes are issued for all 16 possible Device Rows every 15.6 us. Refreshes are issued
whether the DIMMs are populated or not. They are equally spaced in time. The SNC issues REFA
commands on the main channels. The DIMM to be refreshed is specified by the device field of the
REFA command. The SNC will hold off reads and writes to DIMMs that are executing a refresh.
Accesses to other DIMMs can be issued.
5.3.4.1 Serial Control Register Bus
The SCC and DRC registers provide a configuration mechanism to access DMH registers via the
Main Channel Serial I/O (MSIO) bus. The DMH translates this bus to an SPD bus to the DIMMs so
that the DIMMs can be interrogated for size and type.
5.3.4.2 Memory Device Failure Correction
The SNC error correction code described in Section 5.2.5, “Memory Device Failure Correction and
Failure Isolation.” It can correct any data errors from a X4 DDR device. An error in eight out of
every nine X8 devices will be corrected. If more than four errors occur in one out of nine X8
devices, it cannot always be corrected.