Datasheet

Reliability, Availability, and Serviceability
6-4 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
SP Protocol Layer (cont)
P8 Corr Illegal SP Address Error
l
Master abort.
Request
header.
RECSPP
RECSPPD(S
PS)
P10 Corr Received Master Abort Response
m
Master abort.
Response
header.
RECSPP
RECSPPC(S
PS)
Config
C1
e
Fatal
Configuration Multi-Bit DATA ECC
Error (write only)
Register contents not
updated; normal
completion response.
N/A N/A
C2
e
Corr
Configuration Single-Bit DATA ECC
Error (write only)
Correct. N/A N/A
Hub Interface (SIOH)
H1 Fatal
Hub Interface Header Multi-Bit ECC
Error (HI2.0) or Parity Error (HI1.5)
Transaction should be
dropped without
affecting SIOH state.
Header,
parity or
ECC.
NRECHUB
PCISTS
H2 Fatal
Hub Interface – Received
DO_SERR# Message
N/A N/A N/A
H3 Fatal
Illegal Inbound Hub Interface
Request
Request should be
dropped without
affecting SIOH state.
Request
header.
NRECHUB
Unexpected or Invalid response
Response should be
dropped without
affecting SIOH state.
Response
header.
H4 Unc
Received Hub Interface Target
Abort
n
Poison data (reads),
normal completion
(delayed writes).
Response
header.
(HI only)
RECHUB
PCISTS
H5 Unc
Inbound Hub Interface Multi-Bit Data
ECC Error (HI2.0) or Parity Error
(HI1.5)
o
Propagate ECC (HI2.0),
poison data (HI1.5).
Header,
data, parity.
(HI1.5)/ECC
(HI2.0)
RECHUB
REDHUB
PCISTS
H6
e
Unc
Outbound Multi-Bit Data ECC Error
at Hub Interface 1.5 Cluster
p
Poison data. N/A N/A
H7 Corr
Inbound Hub Interface Single Bit
Data ECC Error (HI2.0 only)
o
Propagate ECC.
Header,
data, ECC.
RECHUB
REDHUB
H8 Corr
Received Hub Interface Header
Single Bit ECC Error (HI2.0 only)
Correct. Header RECHUB
H9
e
Corr
Outbound Single Bit Data ECC error
at HI1.5
Correct. N/A N/A
H10 Corr
Hub Interface Illegal Address Error
l
(Inbound)
Master abort.
Request
header.
RECHUB
H11 Corr
Received master abort on Hub
Interface or Unimplemented Special
Cycle
Master abort. N/A
PCISTS,AP
CISTS
a. Decoding errors (unsupported DLEN, etc.).
b. Detected only on processor initiated requests.
c. Transactions are completed on the processor bus without causing SP issue or FWH writes or memory writes. Memory reads
may be issued. Resources such as LATT entries or data buffers may be permanently allocated.
d. HITM# observed on explicit writeback.
Table 6-1. Intel
®
E8870 Chipset Errors (Continued)
ERR# Type Error Name Response Log
Log
Registers