Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 6-5
Reliability, Availability, and Serviceability
6.1.1 End-to-end Error Correction
ECC errors are passed along to the end point. If the data path does not have ECC all the way, single
bit errors will be corrected just before the 1st ECC-less interface. Intermediate interfaces will not
correct single bit ECC errors. The ECC checkbits and parity checkbits are always passed along
with data internally. A typical error will leave a trail behind in each component it passes. The
system can use this to pinpoint source of error and recover from error conditions.
The SNC has the following end points for data:
• Memory:
— Correct single bit error before the data are converted to MDFC ECC on write.
— Store data with poisoned MFDC ECC if multi-bit ECC errors are encountered.
— Correct all correctable errors and convert to good SEC/DED ECC on read.
— Generate poisoned SEC/DED ECC if uncorrectable errors are detected on read.
• SNC FWH (FWH Error Detection is Merged with Processor Bus):
— On outbound cycles, convert to firmware hub (FWH) cycles if no error is detected by
ECC.
— On outbound cycles, drop the transaction if single-bit (1x ECC) or multi-bit ECC (2x
ECC) errors are detected.
— On FWH initiated cycles, generate good ECC.
• Configuration Registers:
— On write, convert to internal configure cycles if no error is detected by ECC.
— On write, convert to internal configure cycles after single bit ECC errors are corrected.
— On write, the write is not performed if an uncorrectable ECC error is detected.
— On read, generate good ECC.
• Partial (8-byte) Write Merge Buffers:
— Merge the buffers and re-generate ECC if no error is detected by ECC.
— Merge the buffers and re-generate ECC after single bit ECC errors are corrected.
— Merge and poison the buffers if multi-bit ECC errors are detected.
e. ECC checking, correction and/or poisoning is done within the 8B boundary of the partial write.
f. FWH slave device indicates error or sync/response handshake in error.
g. Address A[31:3] and transaction type only is logged.
h. Set if no LPC/FWH device drives a valid SYNC after four consecutive clocks.
i. Number of retries logged if LLR is successful.
j. Contents of the error log will be all 0’s if the error cannot be tied to a transaction.
k. There are two instances of strayed transactions. The first is when a response with no matching request is detected. The
second is when the DestNodeId field of the response packet does not match NodeId of the component.
l. This includes access to SP port that is disabled, inbound SP requests with illegal attributes.
m. Provides the ability to detect master abort responses received from the CB or Hub Interface interfaces.
n. Outbound reads only.
o. This error applies to data flowing inbound (inbound write and outbound read completion).
p. This error applies to data flowing outbound (outbound write and inbound read completion).