Datasheet

Introduction
1-4 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
1.4 Interfaces
Figure 1-3 illustrates the SNC and all of its interfaces, which consist of the processor system bus,
four main channels, a firmware hub interface, two scalability ports as well as JTAG and SMBus
ports. The processor system bus interfaces with one to four processors. The two SPs interface to the
scalability port switch or SIOH. Each of the main channels interface to the DMH for DDR-
SDRAM support.
1.4.1 Intel
®
Itanium
®
2 Processor System Bus
The SNC will support up to four Itanium 2 processors. The processor bus consists of 128 bits of
data and 16 bits of ECC. It supports 128-byte cache lines, and with 6.4 GB/s peak bandwidth.
1.4.2 Main Channel
The four main channels on the SNC are extended Direct RAMBUS* channels. The interface has
three row request, five column request, and 18 data signals. Packets up to eight transfers long are
driven on these lines at 800 MT/s. A lower frequency serial chain runs along each channel.
Propagation delays on the main channels can exceed one clock cycle. The channel is divided into
domains of one clock period. When given a serial command, all devices within a domain delay
their transmit data so that it arrives at the domain edge at the same time. Software then determines
the domain of each device by write/read trial and error. Software configures each device with a
coarse delay corresponding to its domain so that data from all devices arrive at the channel master
at the same time.
Figure 1-3. Scalable Node Controller Interfaces
000631a
Itanium
®
2 Processor
400 MHz
6.4 GB/s
800 MHz
6.4 GB/s
SP0
System Bus
Memory Bus
FWH
SMBus
JTAG
Scalability Ports
SP1
800 MHz
6.4 GB/s
SNC
RAC Channels
800 MHz
6.4 GB/s