Datasheet

Reliability, Availability, and Serviceability
6-8 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
• If MDFC is enabled, uncorrectable ECC errors on a memory read will poison the SEC/DED
ECC. For uncorrectable ECC errors detected on memory writes, the MFDC code is poisoned.
• To correct single-bit errors in memory, the memory controller will “walk” the memory,
reading, then writing each location. The interval between each “scrub” is 65536 cycles of 200
MHz clocks. Errors remain in memory until they are scrubbed.
6.1.4.4 Firmware Hub (FWH)
•
ECC in outbound packets is checked at the processor bus.
• FWH has no hardware error protection. Error protection for FWH devices is done through
software CRC or checksum.
6.1.4.5 Configuration Register
•
ECC is checked on configuration writes.
6.1.4.6 Partial Write Merge Buffer
•
ECC is checked before the merge.
6.1.4.7 SMBus
•
The SMBus port supports the optional Packet Error Correction feature. This feature allows the
slave to append an 8-bit CRC to read completions.
6.1.5 Time-Out
6.1.5.1 SIOH
Transactions in the LRB of the SIOH SPP cluster are tracked by timer(s). A time-out transaction is
logged in the error registers as a fatal error. Transactions that time-out are not removed from
internal data structures.
6.1.5.2 SPS
Transactions in SPT of the SPS SPPC cluster are tracked by timer(s). A time-out transaction is
logged in the error registers as a fatal error. Transactions that time-out are not removed from
internal data structures.
6.1.5.3 Timer Implementation
When an entry in the queue is allocated, it becomes valid and is tracked by the master timer logic.
The timer is a 24-bit wrap-around counter, incrementing at 25 MHz (200 MHz core clock divided
by 8). This provides approximately a maximum time-out period of 640 ms. The actual time-out
period is programmable (a value in the ERRCOM register that determines the size of the counter).
The timer interval must be greater than the worst-case latency required in the system to de-allocate
the queue entry. For example, the LATT interval must be set to greater than the worst-case latency
from the SP issue to the response, including contention scenarios for all resources the request must
acquire.