Datasheet
Reliability, Availability, and Serviceability
6-12 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
• Failed PCI slots. Failed PCI slots is isolated by PCI hot-plug hardware.
• Failed P64H2. Failed P64H2 is isolated by disabling the Hub Interface 2.0 interface.
• Failed ICH4. Failed ICH4 is isolated by disabling the Hub Interface 1.5 interface.
6.4 Hot-Plug
Care must be taken on module partitioning to enable maximum RAS. For example, if the two SPS
switches are put on the same module, it is not possible to replace one of them without bringing the
system down. The system vendor is responsible for RAS features on other critical components in
the system, like dual oscillators, fail-over I/O cards, redundant hot-plug power and cooling, etc.
The PCI slots interfaces are all hot-pluggable to provide finer-granularity RAS.
Chipset components reside on Field Replaceable Units (FRU) that are defined by each system
vendor. In this document, these FRUs are referred to as modules to distinguish them from lower-
granularity FRUs such as DIMMs. The E8870 chipset supports the design of a “no-single-point-
failure” system. This is made possible by the chipset modularity and redundancy. In high RAS
configurations, the modules are connected by the SPS switches through the high speed scalability
ports (SPs) that are hot-pluggable. The SPS switches play a central role in the RAS.
This chipset supports hot-plug on SP and PCI. The PCI bus Hot-Plug is done through P64H2. All
hot-plugs are done under the strict control of system software.
6.4.1 Hot-Plug Support on SP
Each SP has the following built-in hot-plug support functions:
• Idle/control packets. Idle and control packets are used in the link level retry, hot-plug and reset.
Idle packets are sent over the SPs whenever the SPs are not in use. Control flits are used during
initialization and framing. The following information is carried in idle and control packet:
— Bus # and device # of the attached device.
— The maximum credit per VC.
— Acknowledgment of receipt of the idle pattern of another device.
— The current FLIT sequence # (used mainly for link-level retry).
— Error indicators.
— No link level retry for next FLIT.
— FLIT sequence # for the 1st bad FLIT.
• A bit to enable/disable SP. When an SP is disabled, its outputs (with the exception of
SPSYNC) are tri-stated and all transactions targeting the SP are master aborted. Note that
disabling/enabling one side of a link causes both sides the SP link to re-initialize and reframe.
• Idle pattern detection. An interrupt can be generated upon change of idle pattern state at
initialization.
• SP{0/1}PRES is used to indicate a present component on the port, and all SP outputs
(including SPSYNC) are tri-stated when SP{0/1}PRES is deasserted. An interrupt can also be
generated upon change of the pin state.The assertion (rising edge) of SP{0/1}PRES also
triggers the SP initialization and framing.
• Two GPIO pins for each SP. Those GPIOs can be used to control additional MUXs or power
circuits.