Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 6-13
Reliability, Availability, and Serviceability
• The ability for system software to generate an interrupt through the SP, and software scratch
bits provided per SP port. This allows system software to use one interrupt for hot-plug
addition and removal sequencing.
• Control and status is provided in a register provided per SP interface. On the SPS, this register
is called the SPINCO register.
• The REMCDEF register on the SPS is used to indicate to the centralized protocol layer the
presence of a component on the port. The SPS uses the contents of this register to determine if
a node should receive a broadcast transaction or a back-invalidate.
• The SIOH provides a mechanism to flush the SIOH write cache. These lines must be flushed
to memory before an SIOH can be hot-removed. Control for flushing the SIOH write cache is
in the IOCTL register.
6.5 Chipset Error Record
This section provides an example of the contents of a chipset error record. The platform error
record consists of a generic header, followed by a number of sections. Each section consists of a
section header followed by a section body. An example section header and body for the E8870
chipset is described here, the chipset using one section. Guidelines for creating the error record are
also provided.
6.5.1 Generating the Error Record
The simplest approach to creating an error record is to read the contents of the FERRST and
SERRST registers in each of the E8870 components in the system. Based on the contents of
FERRST, an error log register is also captured (see Table 6-1 to identify log registers associated
with errors). The FERRST is designed to support status and logging of the first fatal and/or first
non-fatal errors. Once the error status and any associated log registers are captured, errors are
cleared by writing (1’s) to the error bits in SERRST, and FERRST of each component.
It is recommended that the SERRST be cleared before the FERRST so that any subsequent errors
that may occur during the error handling are recorded and logged in the proper order. Also note that
the FERRST/SERRST registers must be cleared for each error for reliable error logging and
parsing.
6.5.2 Chipset Record Section
The chipset section consists of a section header followed by a section body. A section header may
consist of the following fields:
GUID //Globally Unique ID
//128 bits, this value will uniquely identify the E8870 chipset
revision #
section length //bytes, length of header and section body
The chipset section body is organized by function where each function includes a component
header followed by a set of reg_id, reg_value pairs
1
. A single component in the chipset may report
more than one function.
The following is an example of the fields that may be part of the component header:
1. See Table 6-3.