Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 1-5
Introduction
A clock generator must be provided for each channel that is compliant with the Direct RAMBUS
Clock Generator Specification. The SNC will provide a pair of clock phase references for each of
the four main channels. An external clock generator will use these references to generate the
400 MHz differential clock to master (CTM) so that it arrives at the SNC co-incident with the SNC
core clock.
1.4.3 Scalability Port (SP) Interface
The scalability port interface is a high speed interface for connecting the SNC to other chipset
components such as the SIOH. The SP interface serves as a link to I/O when connected to an SIOH.
As the name implies, the SP also allows a system to scale beyond one node. This is done by
connecting a scalability port switch (SPS) to the SNC’s SP interface. Refer to Figure 1-1 “Typical
Itanium
®
2-Based Server Configuration” for example interconnect schemes.
There are two SPs per SNC. Each SP interface contains a Request Out and Response In queue to
pass data to and from the LATT and a Request In and Response Out queue to pass data to and from
the RATT. These queues are 20 entries deep.
The SP uses SBD signaling technology, which allows simultaneous transmission of information in
both directions on the same wire, providing a peak bandwidth of 6.4 GB/s per port (3.2 GB/s in
each direction).
1.4.4 Low Pin Count/Firmware Hub Interface
The SNC interfaces directly to a firmware hub (FWH) component. The low cost FWH interface
comprises four address/data pins (LAD[3:0]) and one framing signal (LFRAME#). Electrically and
with regards to timing, these signals comply with 33 MHz, 3.3V PCI requirements (refer to the PCI
Local Bus Specification, Rev. 2.2).
The firmware hub/low pin count (FWH/LPC) interface supports up to four loads using two clocks,
one clock output per two FWH or LPC components.The SEL_LPC strapping pin selects either the
LPC or FWH protocol for this port.
The SNC supports only slave components. The purpose of this interface is to provide for local
firmware for the processors interfacing to this particular SNC component. Any connected firmware
hub devices must adhere to the Intel
®
82802AB/82802AC Firmware Hub (FWH) Specification.
This interface is only accessible from the processor bus, not the scalability port, JTAG, or SMBus.
The cooperation of a local processor is required to perform firmware updates or check firmware
version.
The LPC features clock speeds of up to 33 MHz and IO/memory/DMA/bus master cycle support.
The LPC interface on the SNC will only support flash devices. The SNC will not tolerate 5V levels
on the LPC interface.
1.4.5 JTAG Interface
This port is used for component configuration and testing. In Boundary Scan testing, system clocks
are not running, so all events are synchronous to the JTAG clock.
In system debug, this port is controlled by the in-target probe (ITP), which is a PCI card driven by
an application running on a PC. JTAG runs asynchronously to the system clocks at no more that
1/8th the bus clock frequency.