Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 6-19
Reliability, Availability, and Serviceability
Hub Interface (SIOH)
H3 Fatal
Illegal Inbound Hub
Interface Request,
Unexpected or Invalid
Response
x xxx x NCS
H4 Unc
Received Hub Interface
Target Abort
src src src CT:2xECC
H5 Unc
Inbound Hub Interface
Multi-Bit Data ECC Error
(HI2.0) or Parity Error
(HI1.5)
src src src src CT:2xECC
H6 Unc
Outbound Multi-Bit Data
ECC Error at HI 1.5
Cluster
end end end CT:2xECC
H7 Corr
Inbound Hub Interface
Single Bit Data ECC Error
(HI2.0 only)
src src src src CT:1xECC
H8 Corr
Received Hub Interface
Header Single Bit ECC
Error (HI2.0 only)
x xxxx x CS
H9 Corr
Outbound Single Bit Data
ECC Error at HI 1.5
end end end CT:1xECC
H10 Corr
Hub Interface Illegal
Address Error
xxx CS
H11 Corr
Received Master Abort on
Hub Interface or
Unimplemented Special
Cycle
src src src CT:MA
a. A memory mapped I/O or I/O transaction.
b. Peer-to-peer write.
c. PLCK, PWNC (attr=INT), PPTC, PEOI, PULCK.
d. Implicit write-back on a snoop.
e. Memory update on implicit write-back.
f. Partial write.
g. N=SNC, S=SPS, I=SIOH.
h. In smart PCI card error model where P64H2 is not programmed to send a DO_SERR special cycle.
i. Headers included on both request and completion packets.
j. Assumes that P64H2 programmed to send a DO_SERR special cycle for ECC errors on outbound data or if PERR#/SERR# observed on PCI
bus. Used in dumb PCI card error model.
Table 6-4. E8870 Chipset Errors, Transaction, and Class Information (Continued)
ERR
#
Type Error Name
Transaction
Error
Class
Proc
read,
coh
Proc
read,
non-
coh
a
Proc
write,
coh
Proc
write,
non-
coha
Read
from
I/O,
coh
Write
from
I/O,
coh
Write
from
I/O
b
SPS
Back
Invali-
date
SPS
Broad-
cast
c
No
Trans-
action