Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 7-1
Clocking 7
7.1 System Clocking
In systems employing the E8870 chipset, the phase of the clock routed to each component can be
arbitrary, although the variation in phase (drift) must be controlled. All of the signals between the
SNC, SPS, and SIOH are source synchronous, or function asynchronously, allowing greater
flexibility in the distribution of the system level clocks.
Agents that have common clock interfaces need clocks delivered in-phase. This condition exists at
the processor bus and the Hub Interface interfaces. The SIOH provides clocks which can be used
by the downstream I/O components (P64H2 and ICH4), and are in phase with SIOH component
core clocks.
7.2 Clock Gearing and Fractional Ratios
There is no support for fractional ratios in the E8870 chipset components. A single clock is used at
each external interface. It is not possible to run the processor bus or HI buses at a frequency
independent of the core or other interfaces. All of these frequencies have fixed ratios to the other
frequencies of the other interfaces. For example, on the SNC the processor bus control signals
work at the same frequency as the core. The SP I/Os always work at 4x that frequency.
Figure 7-1 illustrates the clock distribution scheme the chip set is designed to support.
7.3 Master Clock
The Master System Clock is driven from a central oscillator or frequency synthesizer. A crystal
oscillator is preferred to avoid cascading PLLs. Cascaded PLLs can amplify jitter. The frequency
synthesizer defined for the E8870 chipset supports spread spectrum clocking to minimize EMI.
The clock synthesizer is also capable of operating in non-SSC mode. Nominally this oscillator runs
at 200MHz.
For highly available systems, two Master Oscillators can drive the Master Clock. If the primary
fails, the backup oscillator can be selected by SMBus control.
The Master Clock is distributed to the processor node (processor and SNC), SPSs, and SIOHs
without phase matching. This creates the following timing domains: each node, each SPS, each
SIOH. These domains all run at multiples of the same frequency, but the phase between domains
may vary. The SPs compensate for phase differences between these domains.