Datasheet
Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 7-3
Clocking
Processor and chipset reference clock inputs are differential. Each chipset component has a pair of
differential clock input pins, BUSCLK+ and BUSCLK- on the SNC components, and SYSCLK+
and SYSCLK- on the SIOHs and SPS. These pins are the reference clock inputs for the PLL that
supplies clocks to the core and I/Os. LVHSTL signaling is used. Lengths of processor bus clock
traces must be matched to ensure the processors node bus I/Os are in-phase. Lengths of HI clock
traces must be matched to ensure the SIOH and P64H2/ICH4 I/Os in-phase.
The SNC uses a divided BUSCLK to provide a 25 MHz clock for the common-clocked FWH
components. This clock feeds both sides of the interface. Internal phase synchronizers are used to
synchronize the external interface with the SNC core.
The SIOH uses a regenerated and divided SYSCLK to provide a 66 MHz clock for the common-
clocked Hub Interface buses.
7.4 Itanium
®
2 Processor Bus Clock
7.4.1 Differential Reference Clock (BUSCLK & BUSCLK#)
A 200 MHz common clock, originating from a vendor-supplied system clock generator, is
provided to all processors and the SNC. This is the SNC system bus and Scalability Port reference
clock. This 200 MHz clock is provided in-phase so that the processor bus can achieve maximum
performance. The SNC and processors use this clock to drive and sample system bus common
clock signals. All clocks generated by the SNC such as main memory channels, FWH, processor
bus strobe, and SP transmission clocks are all derived from this clock.
Clock gearing is not be available in the SNC. This means that as the input frequency is increased,
all subsystems must scale in frequency. That includes the SNC core, processor system bus, FWH,
SP, RAC and DRCG/DMCG.
7.5 RAC Clocking Support
Clocking for the RAMBUS ASIC Cell (RAC) in the SNC is provided by the external Direct
RAMBUS Clock Generator (DRCG/DMCG) components. These components require either a
50MHz or 100 MHz single-ended clock source. This clock is provided by the system designer.
Figure 7-2. Differential Bus Clock to Processors and SNC
Buffer
Processor
Processor
SNC
System
Clock
Generator
BUSCLK
BUSCLK#
BUSCLK
BUSCLK#
BUSCLK
BUSCLK#
Clock traces from buffer
to
processors and SNC
must
be delay matched