Datasheet

Introduction
1-6 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
1.4.6 SMBus Slave Interface
This port is controlled by an autonomous platform manager during system operation. The chipset
will support serial data transfers at 100 kHz. The chipset is designed to limit the worst case
probability of metastability on SMBus command transfers to less than one in 10
11
.
1.5 Terminology
Address Bit Permuting Address bits are distributed among channel selects, DRAM
selects and bank selects so that a linear address stream
accesses these resources in a certain sequence.
Bit Interleave The way the bits in a cache line are mapped to channels,
devices, banks, rows, columns (RDRAM) or stacks, banks,
rows, columns (DDR SDRAM) of memory.
Cache Line Interleave The way a series of cache lines are mapped to DRAM
devices.
Critical Word First The SNC will deliver the words of a cache line in a particular
order such that the word addressed in the request appears in
the first data transfer.
DDR SDRAM Double Data Rate SDRAM
DIMM Dual-in-Line Memory Module
DMH DDR Memory Hub
Device Row A set of devices that provide a cache line. Since the second
64 bytes of a 128-byte line are from a page hit on the same
devices, the device row is the same for 64-byte lines and
128-byte lines.
A 4-bit DDR SDRAM device row consists of eight sets of 18
devices that respond to a main channel request. Typically,
these would appear on one side of a DIMM. An 8-bit DDR
SDRAM device row consists of eight sets of nine devices on
each DIMM that respond to a main channel request.
DRAM Page (Row) The DRAM cells selected by the row address.
DRCG/DMCG Direct RAMBUS Clock Generator.
Dirty Node The node which owns a modified cache line.
Direct Connect/Single Node Up to 4-way Intel Itanium 2/ E8870 platform configuration
that consists of one SIOH and SNC that are directly
connected by Scalability Ports.
Explicit Write-Back (EWB) The transaction issued by a processor evicting a cache line.
Home Node The SNC that controls the memory on which a particular
cache line resides.
Host, Processor, CPU The E8870 chipset supports Itanium 2 processor.