Datasheet

Clocking

7-4 Intel

E8870 Scalable Node Controller (SNC) Datasheet

Each Clock Generator requires two phase difference signals from each RAC within the SNC. The

SNC provides a SYNCLK/PCLKN pair for each main channel. The PCLK and SYNCCLK divider

must be cleared by reset to guarantee determinism.

For each main channel, the SNC provides a clock (RxSCK) for serial operations. This clock is

normally 1 MHz, but will change to the SYNCLK frequency (100 MHz) for specific operations.

This clock will be held low from the time PWRGOOD is asserted until after RESETI# rises so that

it does not exceed the specified frequency before PLLs are stabilized.

7.6 DDR SDRAM Clocking Support

All DDR SDRAM clocking support is provided by the DMH component. The DMH converts the

RAC signals of the SNC to interface to DDR SDRAMs. The DRCG/DMCG CTM clocks are used

by the DMH to generate the clocks to the SDRAMs. Refer to the Intel

E8870DH DDR Memory

Hub (DMH) Datasheet for details.

7.7 Firmware Hub Clocking

The FWH device connecting to the SNC requires a 33 MHz common clock signals. This clock is

divided off of the core clock and output from the SNC to an external clock distribution amplifier

with matched output traces to both the SNC and the FWH device.

The 33 MHz clock is provided to both sides of the interface in-phase. This clock is not in-phase

with the core clock. Instead, synchronizers are used for these few signals. Data sampled with the

incoming LCLK is transferred three core clock cycles (nominally 15 ns) after LCLKOUT is driven.

This addresses metastability issues and ensures that FWH reads are deterministic while allowing a

wide range in the length of external clock traces.

Figure 7-3. Firmware Hub Clocks

SET

CLR

Firmware

Hub

Matched External Traces

PLL

33 MHz

SNC