Datasheet

Intel
®
E8870 Scalable Node Controller (SNC) Datasheet 7-5
Clocking
7.8 JTAG
The external TCK is synchronized to the internal core clock for interfacing to the TAP controller
private chains. A metastability-hardened synchronizer is provided for this purpose. TCK interface
to boundary scan uses TCK directly. TCK can be active 10 ms after RESET deassertion. When
inactive, TCK should be deasserted (low). TCK can be clocked from 1 to 20 MHz.
The TCK high time is a minimum of five BUSCLK cycles in duration. The TCK low time is a
minimum of five BUSCLK cycles in duration. This need not be in phase with the BUSCLK for
public chain access.
7.9 SMBus Clocking
The external SMBus clock on the SNC is always a master. It is synchronized to the SNC core
clock. Data driven to the SNC is handled with respect to the serial clock pin SCL. Data received on
the SDA pin with respect to the slave agent’s SCL is synchronized to the core using a metastability-
hardened synchronizer. SCL can be active 10 ms after RESET deassertion. When active, SCL
should be deasserted (high). SCL can be clocked at 100 kHz and 400 kHz.
7.10 Other Functional and Electrical Requirements
7.10.1 Spread Spectrum Support
The E8870 chipset will support Spread Spectrum Clocking (SSC). SSC is a frequency modulation
technique for EMI reduction. Instead of maintaining a constant frequency, SSC modulates the
clock frequency/period along a predetermined path (i.e., the modulation profile). The SNC is
designed to support a nominal modulation frequency of 30 kHz with a downspread percentage of
0.5%.
7.10.2 PLL Lock Time
All chipset PLLs will lock within 1 ms of PWRGOOD assertion. This requires that the differential
BUSCLKs be stable at least 1 ms prior to the assertion of PWRGOOD. The assertion of
PWRGOOD initiates the PLL lock process. External clocks dependent on the PLL are LPC,
memory main channels, SP strobes, and processor bus strobes.
7.11 Analog Power Supply Pins
The SNC uses three PLLs. Each PLL requires an Analog Vcc and Analog Vss pin and external LC
filter.
Note: The filter is NOT to be connected to board Vss. The ground connection of the filter will be routed
through the package and grounded to on-die Vss.