Datasheet

System Reset
8-2 Intel
®
E8870 Scalable Node Controller (SNC) Datasheet
8.2 Reset Sequences
All E8870 chipset reset sequences with the sub-sequences are summarized in Table 8-2.
Table 8-2. Reset Response Sequences Summary
Sequence Begins Ends SNC SPS SIOH
PWRGOOD
Deassertion
When PWRGOOD
falls or as the
power rails rise.
(not possible to
define behavior
prior to power
supplies in spec)
System Logic
asserts
PWRGOOD
Assert RESET# and
LRESET#
N/A Assert RESET66#
Asynchronously clear all logic that can be reset in a single cycle (as
opposed to arrays which require a sequential initialization). Outputs
tristated.
PWRGOOD
Assertion
PWRGOOD rises.
Internal clocks not
stable yet.
RESETI#
deassertion.
Internal clocks
stable.
Continue to clear all logic that can be reset in a single cycle except as
needed to assert required outputs. Configuration bits are set to default
values.
SPS are disabled if
booted from local FWH.
SPs enabled.
Reset any lower
frequency clocks on
exit.
N/A
Reset any lower
frequency clocks on
exit (if DET).
First RESETI#
Deassertion
First time RESETI#
rises after
PWRGOOD is
high.
A few cycles
after it begins.
Sticky Configuration bits are cleared.
Starts divide-by-8 for subsequent RESETI# sampling.
Hard reset deassertion sequence.
Reset references for
lower frequency clocks.
Snoop Filter
initialization.
Reset references for
lower frequency
clocks (if DET).
Hard Reset
Assertion
Section 8.2.2.1
Assertion of:
RESETI# (warm),
SYRE.HardReset,
SYRE.SNCreset,
SYRE.SIOHreset,
BINIT#
Cycle after
sequence
begins.
Configuration bits that are not protected by SYRE.SAVMEM or
SYRE.SAVCFG are set to default values.
SPS are disabled if
booted from local FWH.
SPs enabled.
Clear all logic that can
be reset in a single
cycle except that
covered by
SYRE.SAVCFG or
SYRE.SAVMEM and
sticky configuration bits,
memory maintenance
logic. Any outstanding
RAMBUS operations
must not be interrupted.
Logic that can be cleared in a single cycle is
reset.
Hard Reset
Deassertion
Section 8.2.2
Deassertion of:
Warm Reset,
SYRE.HardReset,
SYRE.SNCreset,
SYRE.SIOHreset,
BINIT#
When
sequence
completes:
101ms max.
Clear all logic except
that covered by
SYRE.SAVCFG or
SYRE.SAVMEM and
sticky configuration bits.
BNR stall. Optional
MEMRST and
CPURST.
Multi-cycle initialization.
Multi-cycle initialization. Clear all logic
except sticky
configuration bits.
Multi-cycle
initialization.
Soft Reset
Section 8.2.3
SNC SYRE. Soft
Reset.
When
sequence
completes.
Assert INIT# None